[llvm] Gate CSR defined by experimental and vendor extensions (PR #104424)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 02:44:20 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-mc
Author: Jesse Huang (jaidTw)
<details>
<summary>Changes</summary>
Currently all CSRs are defined in a single space, and it causes a potential issue that unratified and vendor-customized extensions could have CSR number collide. After diving a bit into the code, I found there already exist a mechanism to specify the required extension for a CSR and check if it is enabled in the assembler.
This patch
1. Set `FeaturesRequired` field for aforementioned CSRs to their providing extensions (And, as for now, only `ssp` provided by Zicfiss(which is experimental) meet this constraint, since we don't have any vendor CSR in the upstream yet)
2. Split experimental CSRs from `user-csr-name.s` test to a new `experimental-csr-names.s` test
3. Make the diagnostic message of lacking a extension for a CSR more detailed. And update related tests
Original: `error: system register use requires an option to be enabled`
New:
- 32-bit only: `error: system register '<csr>' is 32-bit only`
- Lacking extension: `system register '<csr>' requires '<ext>' to be enabled`
- Both: `error: system register '<csr>' is 32-bit only and requires '<ext>' to be enabled`
For the test, we must enumerate all extensions of CSRs in the test in the `-mattr` of `llvm-objdump` until the [mapping symbol patch](https://github.com/llvm/llvm-project/pull/67541) is merged
---
Patch is 48.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/104424.diff
7 Files Affected:
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+21-2)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+17-1)
- (added) llvm/test/MC/RISCV/experimental-csr-names.s (+36)
- (modified) llvm/test/MC/RISCV/machine-csr-names-invalid.s (+33-33)
- (modified) llvm/test/MC/RISCV/rv32-only-csr-names.s (+143-143)
- (modified) llvm/test/MC/RISCV/user-csr-names.s (-14)
``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index a288e7d884d311..03a2e6f19a23a4 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -41,6 +41,7 @@
#include "llvm/TargetParser/RISCVISAInfo.h"
#include <limits>
+#include <numeric>
using namespace llvm;
@@ -1923,8 +1924,26 @@ ParseStatus RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
// Accept a named Sys Reg if the required features are present.
if (SysReg) {
- if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits()))
- return Error(S, "system register use requires an option to be enabled");
+ const auto &FeatureBits = getSTI().getFeatureBits();
+ if (!SysReg->haveRequiredFeatures(FeatureBits)) {
+ const auto *Feature = std::find_if(
+ RISCVFeatureKV, RISCVFeatureKV + RISCV::NumSubtargetFeatures,
+ [&](auto Feature) {
+ return SysReg->FeaturesRequired[Feature.Value];
+ });
+ auto ErrorMsg = std::string("system register '") + SysReg->Name + "' ";
+ if (SysReg->isRV32Only && FeatureBits[RISCV::Feature64Bit]) {
+ ErrorMsg += "is 32-bit only";
+ if (Feature != RISCVFeatureKV + RISCV::NumSubtargetFeatures)
+ ErrorMsg += " and ";
+ }
+ if (Feature != RISCVFeatureKV + RISCV::NumSubtargetFeatures) {
+ ErrorMsg +=
+ "requires '" + std::string(Feature->Key) + "' to be enabled";
+ }
+
+ return Error(S, ErrorMsg);
+ }
Operands.push_back(
RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
return ParseStatus::Success;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e278fa3fe31764..0b28409b4724c3 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -953,7 +953,7 @@ def FeatureStdExtSstc
: RISCVExtension<"sstc", 1, 0,
"'Sstc' (Supervisor-mode timer interrupts)">;
-def FeaturesStdExtSsqosid
+def FeatureStdExtSsqosid
: RISCVExperimentalExtension<"ssqosid", 1, 0,
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index a836227e18957c..5a70daee614152 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -82,6 +82,7 @@ def SysRegFCSR : SysReg<"fcsr", 0x003>;
//===----------------------------------------------------------------------===//
// User Counter/Timers
//===----------------------------------------------------------------------===//
+
def CYCLE : SysReg<"cycle", 0xC00>;
def TIME : SysReg<"time", 0xC01>;
def INSTRET : SysReg<"instret", 0xC02>;
@@ -103,6 +104,7 @@ foreach i = 3...31 in
//===----------------------------------------------------------------------===//
// Supervisor Trap Setup
//===----------------------------------------------------------------------===//
+
def : SysReg<"sstatus", 0x100>;
def : SysReg<"sie", 0x104>;
def : SysReg<"stvec", 0x105>;
@@ -120,6 +122,7 @@ def : SysReg<"senvcfg", 0x10A>;
//===----------------------------------------------------------------------===//
// Supervisor Trap Handling
//===----------------------------------------------------------------------===//
+
def : SysReg<"sscratch", 0x140>;
def : SysReg<"sepc", 0x141>;
def : SysReg<"scause", 0x142>;
@@ -130,12 +133,14 @@ def : SysReg<"sip", 0x144>;
//===----------------------------------------------------------------------===//
// Supervisor Protection and Translation
//===----------------------------------------------------------------------===//
+
let DeprecatedName = "sptbr" in
def : SysReg<"satp", 0x180>;
//===----------------------------------------------------------------------===//
// Quality-of-Service(QoS) Identifiers (Ssqosid)
//===----------------------------------------------------------------------===//
+
def : SysReg<"srmcfg", 0x181>;
//===----------------------------------------------------------------------===//
@@ -229,6 +234,7 @@ def : SysReg<"mconfigptr", 0xF15>;
//===----------------------------------------------------------------------===//
// Machine Trap Setup
//===----------------------------------------------------------------------===//
+
def : SysReg<"mstatus", 0x300>;
def : SysReg<"misa", 0x301>;
def : SysReg<"medeleg", 0x302>;
@@ -242,6 +248,7 @@ def : SysReg<"mstatush", 0x310>;
//===----------------------------------------------------------------------===//
// Machine Trap Handling
//===----------------------------------------------------------------------===//
+
def : SysReg<"mscratch", 0x340>;
def : SysReg<"mepc", 0x341>;
def : SysReg<"mcause", 0x342>;
@@ -279,6 +286,7 @@ foreach i = 0...63 in
//===----------------------------------------------------------------------===//
// Machine Counter and Timers
//===----------------------------------------------------------------------===//
+
def : SysReg<"mcycle", 0xB00>;
def : SysReg<"minstret", 0xB02>;
@@ -298,6 +306,7 @@ foreach i = 3...31 in
//===----------------------------------------------------------------------===//
// Machine Counter Setup
//===----------------------------------------------------------------------===//
+
let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
def : SysReg<"mcountinhibit", 0x320>;
@@ -314,11 +323,13 @@ foreach i = 3...31 in {
//===----------------------------------------------------------------------===//
// Supervisor Counter Setup
//===----------------------------------------------------------------------===//
+
def : SysReg<"scountinhibit", 0x120>;
//===----------------------------------------------------------------------===//
// Debug/ Trace Registers (shared with Debug Mode)
//===----------------------------------------------------------------------===//
+
def : SysReg<"tselect", 0x7A0>;
def : SysReg<"tdata1", 0x7A1>;
def : SysReg<"tdata2", 0x7A2>;
@@ -328,6 +339,7 @@ def : SysReg<"mcontext", 0x7A8>;
//===----------------------------------------------------------------------===//
// Debug Mode Registers
//===----------------------------------------------------------------------===//
+
def : SysReg<"dcsr", 0x7B0>;
def : SysReg<"dpc", 0x7B1>;
@@ -340,6 +352,7 @@ def : SysReg<"dscratch1", 0x7B3>;
//===----------------------------------------------------------------------===//
// User Vector CSRs
//===----------------------------------------------------------------------===//
+
def : SysReg<"vstart", 0x008>;
def : SysReg<"vxsat", 0x009>;
def SysRegVXRM : SysReg<"vxrm", 0x00A>;
@@ -351,7 +364,10 @@ def SysRegVLENB: SysReg<"vlenb", 0xC22>;
//===----------------------------------------------------------------------===//
// Shadow Stack CSR
//===----------------------------------------------------------------------===//
-def : SysReg<"ssp", 0x011>;
+
+let FeaturesRequired = [{ {RISCV::FeatureStdExtZicfiss} }] in {
+ def : SysReg<"ssp", 0x011>;
+}
//===----------------------------------------------------------------------===//
// State Enable Extension (Smstateen)
diff --git a/llvm/test/MC/RISCV/experimental-csr-names.s b/llvm/test/MC/RISCV/experimental-csr-names.s
new file mode 100644
index 00000000000000..e1b3f7c93b287a
--- /dev/null
+++ b/llvm/test/MC/RISCV/experimental-csr-names.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zicfiss - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zicfiss - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-INVALID %s
+
+##################################
+# Experimental User CSRs
+##################################
+
+.option push
+.option arch, +zicfiss
+# ssp
+# name
+# CHECK-INST: csrrs t1, ssp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x01]
+# CHECK-INST-ALIAS: csrr t1, ssp
+# uimm12
+# CHECK-INST: csrrs t2, ssp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x01]
+# CHECK-INST-ALIAS: csrr t2, ssp
+# name
+# CHECK-INVALID: error: unexpected experimental extensions
+csrrs t1, ssp, zero # CHECK-INVALID: :[[@LINE]]:11: error: system register 'ssp' requires 'experimental-zicfiss' to be enabled
+# uimm12
+csrrs t2, 0x011, zero
+.option pop
diff --git a/llvm/test/MC/RISCV/machine-csr-names-invalid.s b/llvm/test/MC/RISCV/machine-csr-names-invalid.s
index 9afb6d7744a8df..c9d43668a1b7b7 100644
--- a/llvm/test/MC/RISCV/machine-csr-names-invalid.s
+++ b/llvm/test/MC/RISCV/machine-csr-names-invalid.s
@@ -3,38 +3,38 @@
# These machine mode CSR register names are RV32 only.
-csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg1' is 32-bit only
+csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg3' is 32-bit only
-csrrs t1, mcycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, minstreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mcycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mcycleh' is 32-bit only
+csrrs t1, minstreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'minstreth' is 32-bit only
-csrrs t1, mhpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, mhpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter3h' is 32-bit only
+csrrs t1, mhpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter4h' is 32-bit only
+csrrs t1, mhpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter5h' is 32-bit only
+csrrs t1, mhpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter6h' is 32-bit only
+csrrs t1, mhpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter7h' is 32-bit only
+csrrs t1, mhpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter8h' is 32-bit only
+csrrs t1, mhpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter9h' is 32-bit only
+csrrs t1, mhpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter10h' is 32-bit only
+csrrs t1, mhpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter11h' is 32-bit only
+csrrs t1, mhpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter12h' is 32-bit only
+csrrs t1, mhpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter13h' is 32-bit only
+csrrs t1, mhpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter14h' is 32-bit only
+csrrs t1, mhpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter15h' is 32-bit only
+csrrs t1, mhpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter16h' is 32-bit only
+csrrs t1, mhpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter17h' is 32-bit only
+csrrs t1, mhpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter18h' is 32-bit only
+csrrs t1, mhpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter19h' is 32-bit only
+csrrs t1, mhpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter20h' is 32-bit only
+csrrs t1, mhpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter21h' is 32-bit only
+csrrs t1, mhpmcounter22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter22h' is 32-bit only
+csrrs t1, mhpmcounter23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter23h' is 32-bit only
+csrrs t1, mhpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter24h' is 32-bit only
+csrrs t1, mhpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter25h' is 32-bit only
+csrrs t1, mhpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter26h' is 32-bit only
+csrrs t1, mhpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter27h' is 32-bit only
+csrrs t1, mhpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter28h' is 32-bit only
+csrrs t1, mhpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter29h' is 32-bit only
+csrrs t1, mhpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter30h' is 32-bit only
+csrrs t1, mhpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mhpmcounter31h' is 32-bit only
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index 5a91aea4c791b2..fcc0fc146dfd55 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -3,146 +3,146 @@
# The following CSR register names are all RV32 only.
-csrrs t1, cycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, timeh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, instreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-
-csrrs t1, hpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, hpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabl...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/104424
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