[llvm] RISC-V: Add fminimumnum and fmaximumnum support (PR #104411)

[Craig Topper via llvm-commits]

================
@@ -16468,7 +16476,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::SMAX:
   case ISD::SMIN:
   case ISD::FMAXNUM:
-  case ISD::FMINNUM: {
+  case ISD::FMINNUM:
----------------
topperc wrote:

This isn’t tested

https://github.com/llvm/llvm-project/pull/104411