[llvm] RISC-V: Add fminimumnum and fmaximumnum support (PR #104411)

[Craig Topper via llvm-commits]

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@@ -1394,7 +1401,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::SRA);
 
   if (Subtarget.hasStdExtFOrZfinx())
-    setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM, ISD::FMUL});
+    setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM,
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topperc wrote:

This isn’t tested

https://github.com/llvm/llvm-project/pull/104411