[llvm] [LegalizeTypes][AMDGPU]: Allow for scalarization of insert_subvector (PR #104236)
Jeffrey Byrnes via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 14 20:01:14 PDT 2024
https://github.com/jrbyrnes updated https://github.com/llvm/llvm-project/pull/104236
>From 77837b3d593bcbc2c86f64e68afe66c6f09c3bf8 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Wed, 14 Aug 2024 13:18:20 -0700
Subject: [PATCH 1/4] [LegalizeTypes][AMDGPU]: Allow for scalarization of
insert_subvector
Change-Id: I4c027ef7b44d8ac3d628ad44be50d1cc9eda45d3
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 12 +++++++++
.../AMDGPU/scalarize-insert-subvector.ll | 26 +++++++++++++++++++
3 files changed, 39 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 3a49a8ff10860a..328f567e24e567 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
+ SDValue ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecOp_VSELECT(SDNode *N);
SDValue ScalarizeVecOp_VSETCC(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 5a21ad7ac7e2cd..d8f915ade862ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -765,6 +765,9 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::CONCAT_VECTORS:
Res = ScalarizeVecOp_CONCAT_VECTORS(N);
break;
+ case ISD::INSERT_SUBVECTOR:
+ Res = ScalarizeVecOp_INSERT_SUBVECTOR(N, OpNo);
+ break;
case ISD::EXTRACT_VECTOR_ELT:
Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
break;
@@ -882,6 +885,15 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
}
+/// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
+SDValue DAGTypeLegalizer::ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N,
+ unsigned OpNo) {
+ auto Elt = GetScalarizedVector(N->getOperand(OpNo));
+ auto VecOp = N->getOperand(1 - OpNo);
+ return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecOp.getValueType(),
+ VecOp, Elt, N->getOperand(2));
+}
+
/// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
/// so just return the element, ignoring the index.
SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
diff --git a/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll b/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
new file mode 100644
index 00000000000000..b74bb9b597c3c3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+
+define void @scalarize_insert_subvector(ptr addrspace(3) %inptr, ptr addrspace(3) %inptr1, ptr addrspace(3) %outptr) {
+; GCN-LABEL: scalarize_insert_subvector:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: ds_read_b64 v[4:5], v0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: ds_read_b32 v5, v1 offset:4
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: ds_write_b64 v2, v[4:5]
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %load0 = load <2 x i32>, ptr addrspace(3) %inptr, align 8
+ %load1= load <2 x i32>, ptr addrspace(3) %inptr1, align 8
+ %shuffle0 = shufflevector <2 x i32> %load1, <2 x i32> poison, <1 x i32> <i32 1>
+ %bitcast0 = bitcast <1 x i32> %shuffle0 to <2 x half>
+ %bitcast1 = bitcast <2 x i32> %load0 to <4 x half>
+ %shuffle1 = shufflevector <2 x half> %bitcast0, <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+ %shuffle2 = shufflevector <4 x half> %bitcast1, <4 x half> %shuffle1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+ store <4 x half> %shuffle2, ptr addrspace(3) %outptr
+ ret void
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}
>From 7a74c28370cf19d10a05d862ec5ef43eed70505a Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Wed, 14 Aug 2024 13:59:13 -0700
Subject: [PATCH 2/4] Fix comment
Change-Id: I0275775976a6adea871dae817f54708230376076
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index d8f915ade862ed..461d68c11269de 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -885,7 +885,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
}
-/// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
+/// The inserted subvector is to be scalarized - use insert vector element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N,
unsigned OpNo) {
auto Elt = GetScalarizedVector(N->getOperand(OpNo));
>From ab8a11cf9470a57ab26602cc0be39cfbbb35bcc3 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Wed, 14 Aug 2024 14:38:38 -0700
Subject: [PATCH 3/4] Formatting
Change-Id: I4ad933803db0c0a0bc4d1ab78ef1605c62fcee1f
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 461d68c11269de..ebab6f7fc182be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -885,7 +885,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
}
-/// The inserted subvector is to be scalarized - use insert vector element instead.
+/// The inserted subvector is to be scalarized - use insert vector element
+/// instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N,
unsigned OpNo) {
auto Elt = GetScalarizedVector(N->getOperand(OpNo));
>From 1f1436eddb670c690cbec21e67cd8a324b6d813b Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Wed, 14 Aug 2024 20:00:03 -0700
Subject: [PATCH 4/4] Fix test
Change-Id: I63627d230113ddb2fbf726ac9db868831d0a33e7
---
llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll b/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
index b74bb9b597c3c3..1644c41353752c 100644
--- a/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GCN %s
define void @scalarize_insert_subvector(ptr addrspace(3) %inptr, ptr addrspace(3) %inptr1, ptr addrspace(3) %outptr) {
; GCN-LABEL: scalarize_insert_subvector:
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