[llvm] abaa531 - [RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 14 19:37:08 PDT 2024
Author: LiqinWeng
Date: 2024-08-15T10:37:04+08:00
New Revision: abaa53199ed03b2e9de9fd373cbcfcc88e5348ff
URL: https://github.com/llvm/llvm-project/commit/abaa53199ed03b2e9de9fd373cbcfcc88e5348ff
DIFF: https://github.com/llvm/llvm-project/commit/abaa53199ed03b2e9de9fd373cbcfcc88e5348ff.diff
LOG: [RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
This optimization helps reduce repeated calculations of base addresses
by extracting type extensions when the same base address is accessed
multiple times but its offset is a constant.
Added:
llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 02f48d41b56b3..911fa45d7173e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1428,6 +1428,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Disable strict node mutation.
IsStrictFPEnabled = true;
+ EnableExtLdPromotion = true;
// Let the subtarget decide if a predictable select is more expensive than the
// corresponding branch. This information is used in CGP/SelectOpt to decide
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 85683c6206443..781e3d7929aa4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2000,3 +2000,35 @@ bool RISCVTTIImpl::areInlineCompatible(const Function *Caller,
// target-features.
return (CallerBits & CalleeBits) == CalleeBits;
}
+
+/// See if \p I should be considered for address type promotion. We check if \p
+/// I is a sext with right type and used in memory accesses. If it used in a
+/// "complex" getelementptr, we allow it to be promoted without finding other
+/// sext instructions that sign extended the same initial value. A getelementptr
+/// is considered as "complex" if it has more than 2 operands.
+bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
+ const Instruction &I, bool &AllowPromotionWithoutCommonHeader) {
+ bool Considerable = false;
+ AllowPromotionWithoutCommonHeader = false;
+ if (!isa<SExtInst>(&I))
+ return false;
+ Type *ConsideredSExtType =
+ Type::getInt64Ty(I.getParent()->getParent()->getContext());
+ if (I.getType() != ConsideredSExtType)
+ return false;
+ // See if the sext is the one with the right type and used in at least one
+ // GetElementPtrInst.
+ for (const User *U : I.users()) {
+ if (const GetElementPtrInst *GEPInst = dyn_cast<GetElementPtrInst>(U)) {
+ Considerable = true;
+ // A getelementptr is considered as "complex" if it has more than 2
+ // operands. We will promote a SExt used in such complex GEP as we
+ // expect some computation to be merged if they are done on 64 bits.
+ if (GEPInst->getNumOperands() > 2) {
+ AllowPromotionWithoutCommonHeader = true;
+ break;
+ }
+ }
+ }
+ return Considerable;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 9c37a4f6ec2d0..f5eca2839acd0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -397,7 +397,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
bool shouldFoldTerminatingConditionAfterLSR() const {
return true;
}
-
+ bool
+ shouldConsiderAddressTypePromotion(const Instruction &I,
+ bool &AllowPromotionWithoutCommonHeader);
std::optional<unsigned> getMinPageSize() const { return 4096; }
};
diff --git a/llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll b/llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll
new file mode 100644
index 0000000000000..b733c6a1c787b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -S | FileCheck %s
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "riscv64"
+
+%struct.match_state = type { i64, i64 }
+
+; %add is also promoted by forking an extra sext.
+define void @promoteTwoOne(i32 %i, i32 %j, ptr %P1, ptr %P2 ) {
+; CHECK-LABEL: define void @promoteTwoOne(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[S2:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[J]] to i64
+; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[S2]], [[PROMOTED2]]
+; CHECK-NEXT: [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
+; CHECK-NEXT: store i64 [[S]], ptr [[ADDR1]], align 8
+; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
+; CHECK-NEXT: store i64 [[S2]], ptr [[ADDR2]], align 8
+; CHECK-NEXT: ret void
+;
+entry:
+ %add = add nsw i32 %i, %j
+ %s = sext i32 %add to i64
+ %addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
+ store i64 %s, ptr %addr1
+ %s2 = sext i32 %i to i64
+ %addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
+ store i64 %s2, ptr %addr2
+ ret void
+}
+
+; Both %add1 and %add2 are promoted by forking extra sexts.
+define void @promoteTwoTwo(i32 %i, i32 %j, i32 %k, ptr %P1, ptr %P2) {
+; CHECK-LABEL: define void @promoteTwoTwo(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], i32 [[K:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[PROMOTED3:%.*]] = sext i32 [[J]] to i64
+; CHECK-NEXT: [[PROMOTED4:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED4]]
+; CHECK-NEXT: [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
+; CHECK-NEXT: store i64 [[S]], ptr [[ADDR1]], align 8
+; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[K]] to i64
+; CHECK-NEXT: [[S2:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED2]]
+; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
+; CHECK-NEXT: store i64 [[S2]], ptr [[ADDR2]], align 8
+; CHECK-NEXT: ret void
+;
+entry:
+ %add1 = add nsw i32 %j, %i
+ %s = sext i32 %add1 to i64
+ %addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
+ store i64 %s, ptr %addr1
+ %add2 = add nsw i32 %j, %k
+ %s2 = sext i32 %add2 to i64
+ %addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
+ store i64 %s2, ptr %addr2
+ ret void
+}
+
+define i64 @promoteGEPSunk(i1 %cond, ptr %base, i32 %i) {
+; CHECK-LABEL: define i64 @promoteGEPSunk(
+; CHECK-SAME: i1 [[COND:%.*]], ptr [[BASE:%.*]], i32 [[I:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[PROMOTED1:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[PROMOTED1]], 1
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S]]
+; CHECK-NEXT: [[S2:%.*]] = add nsw i64 [[PROMOTED1]], 2
+; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S2]]
+; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_THEN2:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load i64, ptr [[ADDR]], align 8
+; CHECK-NEXT: [[V2:%.*]] = load i64, ptr [[ADDR2]], align 8
+; CHECK-NEXT: [[R:%.*]] = add i64 [[V]], [[V2]]
+; CHECK-NEXT: ret i64 [[R]]
+; CHECK: if.then2:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %add = add nsw i32 %i, 1
+ %s = sext i32 %add to i64
+ %addr = getelementptr inbounds i64, ptr %base, i64 %s
+ %add2 = add nsw i32 %i, 2
+ %s2 = sext i32 %add2 to i64
+ %addr2 = getelementptr inbounds i64, ptr %base, i64 %s2
+ br i1 %cond, label %if.then, label %if.then2
+if.then:
+ %v = load i64, ptr %addr
+ %v2 = load i64, ptr %addr2
+ %r = add i64 %v, %v2
+ ret i64 %r
+if.then2:
+ ret i64 0;
+}
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