[llvm] 3265dfe - [RISCV] Add signext attribute to return of fmv_x_w test in float-convert.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 14 14:32:45 PDT 2024
Author: Craig Topper
Date: 2024-08-14T14:32:38-07:00
New Revision: 3265dfe3e620d526ca15dcecaa1c68e63ceaba45
URL: https://github.com/llvm/llvm-project/commit/3265dfe3e620d526ca15dcecaa1c68e63ceaba45
DIFF: https://github.com/llvm/llvm-project/commit/3265dfe3e620d526ca15dcecaa1c68e63ceaba45.diff
LOG: [RISCV] Add signext attribute to return of fmv_x_w test in float-convert.ll. NFC
This shows that Zfinx generates a sext.w instruction on RV64.
The fadd.s should have filled the upper bits of the GPR with sign
bits so this is unnecessary. Proving it is unnecessary might be
difficult though.
Added:
Modified:
llvm/test/CodeGen/RISCV/float-convert.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 21bf6618c52a26..805ddee4ac3f6f 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -336,17 +336,23 @@ start:
}
declare i32 @llvm.fptoui.sat.i32.f32(float)
-define i32 @fmv_x_w(float %a, float %b) nounwind {
+define signext i32 @fmv_x_w(float %a, float %b) nounwind {
; CHECKIF-LABEL: fmv_x_w:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fadd.s fa5, fa0, fa1
; CHECKIF-NEXT: fmv.x.w a0, fa5
; CHECKIF-NEXT: ret
;
-; CHECKIZFINX-LABEL: fmv_x_w:
-; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: fadd.s a0, a0, a1
-; CHECKIZFINX-NEXT: ret
+; RV32IZFINX-LABEL: fmv_x_w:
+; RV32IZFINX: # %bb.0:
+; RV32IZFINX-NEXT: fadd.s a0, a0, a1
+; RV32IZFINX-NEXT: ret
+;
+; RV64IZFINX-LABEL: fmv_x_w:
+; RV64IZFINX: # %bb.0:
+; RV64IZFINX-NEXT: fadd.s a0, a0, a1
+; RV64IZFINX-NEXT: sext.w a0, a0
+; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: fmv_x_w:
; RV32I: # %bb.0:
@@ -362,6 +368,7 @@ define i32 @fmv_x_w(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __addsf3
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
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