[llvm] [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (PR #101751)

[Craig Topper via llvm-commits]

topperc wrote:

> Can you have a look at the following regression (extracted from velox):
> 
> ```
> ; bin/llc -mtriple=riscv64 -mattr=+zba test.ll -o -
> 
> define ptr @func0000000000000004(ptr %0, i64 %1) nounwind {
> entry:
>   %2 = ashr i64 %1, 32
>   %3 = lshr i64 %2, 6
>   %4 = getelementptr i64, ptr %0, i64 %3
>   ret ptr %4
> }
> ```
> 
> Before:
> 
> ```
> func0000000000000004:
>         srai    a1, a1, 32
>         srli    a1, a1, 6
>         sh3add  a0, a1, a0
>         ret
> ```
> 
> After applying this patch:
> 
> ```
> func0000000000000004:
>         srai    a1, a1, 35
>         li      a2, -57
>         srli    a2, a2, 3
>         and     a1, a1, a2
>         add     a0, a0, a1
>         ret
> ```

Will do

https://github.com/llvm/llvm-project/pull/101751