[llvm] [RISCV][doc] Add note to RISCVUsage about supported atomics ABIs (PR #103879)

[Paul Kirth via llvm-commits]

================
@@ -280,6 +280,11 @@ Supported
 ``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
   These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__.  They do not introduce any new features themselves, but instead describe existing hardware features.
 
+Atomics ABIs
+============
+
+At the time of writing there are three atomics mappings (ABIs) `defined for RISC-V <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version>__`.  As of LLVM 19, LLVM defaults to "A6S", which is compatible with both the original "A6" and the future "A7" ABI. See `the psABI atomics document <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc>`__ for more information on these mappings.
+
----------------
ilovepi wrote:

I think we should add some verbiage about the attributes being off by default. It may be worth explaining why. 

Perhaps something along the lines of: “While we generate code for the A6S ABI, because support for them across Linkers is unclear, we do not yet emit the corresponding ELF attributes by default. These require a backend flag to enable, and , to our knowledge, are only supported by LLD. “

I’m not tied to any of that, so feel free to edit. 


https://github.com/llvm/llvm-project/pull/103879