[llvm] 3efcc8e - [LV] Add test where diff checks not used when re-trying with RT checks.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2024-08-14T14:19:35+01:00
New Revision: 3efcc8ec7d7e3ed3c7a4bc3ca4bb4ba66adc7e2b

URL: https://github.com/llvm/llvm-project/commit/3efcc8ec7d7e3ed3c7a4bc3ca4bb4ba66adc7e2b
DIFF: https://github.com/llvm/llvm-project/commit/3efcc8ec7d7e3ed3c7a4bc3ca4bb4ba66adc7e2b.diff

LOG: [LV] Add test where diff checks not used when re-trying with RT checks.

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
index 55bbf54d1f39d..35ece2fe6eacd 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -passes=loop-vectorize -hoist-runtime-checks=false -force-vector-width=4 -force-vector-interleave=1 -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
@@ -320,3 +319,61 @@ inner.exit:
 outer.exit:
   ret void
 }
+
+define void @use_
diff _checks_when_retrying_with_rt_checks(i64 %off, ptr %dst, ptr %src) {
+; CHECK-LABEL: @use_
diff _checks_when_retrying_with_rt_checks(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 false, label %scalar.ph, label %vector.memcheck
+; CHECK:       vector.memcheck:
+; CHECK-NEXT:    [[TMP0:%.*]] = shl i64 %off, 3
+; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr %dst, i64 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 8000
+; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr %dst, i64 [[TMP1]]
+; CHECK-NEXT:    [[SCEVGEP2:%.*]] = getelementptr i8, ptr %dst, i64 8000
+; CHECK-NEXT:    [[SCEVGEP3:%.*]] = getelementptr i8, ptr %src, i64 8000
+; CHECK-NEXT:    [[SCEVGEP4:%.*]] = getelementptr i8, ptr %src, i64 8
+; CHECK-NEXT:    [[SCEVGEP5:%.*]] = getelementptr i8, ptr %src, i64 8008
+; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP2]]
+; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr %dst, [[SCEVGEP1]]
+; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT:    [[BOUND06:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP3]]
+; CHECK-NEXT:    [[BOUND17:%.*]] = icmp ult ptr %src, [[SCEVGEP1]]
+; CHECK-NEXT:    [[FOUND_CONFLICT8:%.*]] = and i1 [[BOUND06]], [[BOUND17]]
+; CHECK-NEXT:    [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT8]]
+; CHECK-NEXT:    [[BOUND09:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP5]]
+; CHECK-NEXT:    [[BOUND110:%.*]] = icmp ult ptr [[SCEVGEP4]], [[SCEVGEP1]]
+; CHECK-NEXT:    [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]]
+; CHECK-NEXT:    [[CONFLICT_RDX12:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT11]]
+; CHECK-NEXT:    [[BOUND013:%.*]] = icmp ult ptr %dst, [[SCEVGEP3]]
+; CHECK-NEXT:    [[BOUND114:%.*]] = icmp ult ptr %src, [[SCEVGEP2]]
+; CHECK-NEXT:    [[FOUND_CONFLICT15:%.*]] = and i1 [[BOUND013]], [[BOUND114]]
+; CHECK-NEXT:    [[CONFLICT_RDX16:%.*]] = or i1 [[CONFLICT_RDX12]], [[FOUND_CONFLICT15]]
+; CHECK-NEXT:    [[BOUND017:%.*]] = icmp ult ptr %dst, [[SCEVGEP5]]
+; CHECK-NEXT:    [[BOUND118:%.*]] = icmp ult ptr [[SCEVGEP4]], [[SCEVGEP2]]
+; CHECK-NEXT:    [[FOUND_CONFLICT19:%.*]] = and i1 [[BOUND017]], [[BOUND118]]
+; CHECK-NEXT:    [[CONFLICT_RDX20:%.*]] = or i1 [[CONFLICT_RDX16]], [[FOUND_CONFLICT19]]
+; CHECK-NEXT:    br i1 [[CONFLICT_RDX20]], label %scalar.ph, label %vector.ph
+; CHECK:       vector.ph:
+; CHECK-NEXT:    br label %vector.body
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %iv.off = add i64 %off, %iv
+  %gep.src = getelementptr i64, ptr %src, i64 %iv
+  %l.0 = load i64, ptr %gep.src, align 8
+  %gep.dst.off = getelementptr i64, ptr %dst, i64 %iv.off
+  store i64 %l.0, ptr %gep.dst.off, align 8
+  %gep.src.8 = getelementptr i8, ptr %gep.src, i64 8
+  %l.1 = load i64, ptr %gep.src.8, align 8
+  %gep.dst.iv = getelementptr i64, ptr %dst, i64 %iv
+  store i64 %l.1, ptr %gep.dst.iv, align 8
+  %iv.next = add i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}