[llvm] [RISC-V][HWASAN] Allow disabling short granules (PR #103729)
Samuel Holland via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 14 02:26:07 PDT 2024
https://github.com/SiFiveHolland created https://github.com/llvm/llvm-project/pull/103729
Linux kernel HWASAN does not use them.
Currently, disabling short granules causes an ICE.
>From c0513ddc25613a63fb2451797fc319ca6be6b8f0 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel.holland at sifive.com>
Date: Fri, 2 Aug 2024 16:30:09 -0700
Subject: [PATCH] [RISC-V][HWASAN] Allow disabling short granules
Linux kernel HWASAN does not use them.
---
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 101 ++++++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 7 ++
2 files changed, 62 insertions(+), 46 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 93677433c04405..902c08bb48dd40 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -87,7 +87,7 @@ class RISCVAsmPrinter : public AsmPrinter {
bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
- typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
+ typedef std::tuple<unsigned, bool, uint32_t> HwasanMemaccessTuple;
std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
void LowerKCFI_CHECK(const MachineInstr &MI);
@@ -297,6 +297,7 @@ void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
switch (MI->getOpcode()) {
+ case RISCV::HWASAN_CHECK_MEMACCESS:
case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
LowerHWASAN_CHECK_MEMACCESS(*MI);
return;
@@ -510,16 +511,19 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
Register Reg = MI.getOperand(0).getReg();
+ bool IsShort = MI.getOpcode() == RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
uint32_t AccessInfo = MI.getOperand(1).getImm();
MCSymbol *&Sym =
- HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
+ HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, IsShort, AccessInfo)];
if (!Sym) {
// FIXME: Make this work on non-ELF.
if (!TM.getTargetTriple().isOSBinFormatELF())
report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
- std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +
- utostr(AccessInfo) + "_short";
+ std::string SymName =
+ "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + utostr(AccessInfo);
+ if (IsShort)
+ SymName += "_short";
Sym = OutContext.getOrCreateSymbol(SymName);
}
auto Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, OutContext);
@@ -639,7 +643,8 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
for (auto &P : HwasanMemaccessSymbols) {
unsigned Reg = std::get<0>(P.first);
- uint32_t AccessInfo = std::get<1>(P.first);
+ bool IsShort = std::get<1>(P.first);
+ uint32_t AccessInfo = std::get<2>(P.first);
MCSymbol *Sym = P.second;
unsigned Size =
@@ -694,50 +699,54 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
MCSTI);
OutStreamer->emitLabel(HandleMismatchOrPartialSym);
- OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
- .addReg(RISCV::X28)
- .addReg(RISCV::X0)
- .addImm(16),
- MCSTI);
- MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BGEU)
- .addReg(RISCV::X6)
- .addReg(RISCV::X28)
- .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
- MCSTI);
-
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
- MCSTI);
-
- if (Size != 1)
+ if (IsShort) {
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
.addReg(RISCV::X28)
- .addReg(RISCV::X28)
- .addImm(Size - 1),
+ .addReg(RISCV::X0)
+ .addImm(16),
MCSTI);
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BGE)
- .addReg(RISCV::X28)
- .addReg(RISCV::X6)
- .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
- MCSTI);
-
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
- MCSTI);
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
- MCSTI);
- OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BEQ)
- .addReg(RISCV::X6)
- .addReg(RISCV::X7)
- .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
- MCSTI);
-
- OutStreamer->emitLabel(HandleMismatchSym);
+ MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
+ OutStreamer->emitInstruction(
+ MCInstBuilder(RISCV::BGEU)
+ .addReg(RISCV::X6)
+ .addReg(RISCV::X28)
+ .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
+ MCSTI);
+
+ OutStreamer->emitInstruction(
+ MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
+ MCSTI);
+
+ if (Size != 1)
+ OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
+ .addReg(RISCV::X28)
+ .addReg(RISCV::X28)
+ .addImm(Size - 1),
+ MCSTI);
+ OutStreamer->emitInstruction(
+ MCInstBuilder(RISCV::BGE)
+ .addReg(RISCV::X28)
+ .addReg(RISCV::X6)
+ .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
+ MCSTI);
+
+ OutStreamer->emitInstruction(
+ MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
+ MCSTI);
+ OutStreamer->emitInstruction(MCInstBuilder(RISCV::LBU)
+ .addReg(RISCV::X6)
+ .addReg(RISCV::X6)
+ .addImm(0),
+ MCSTI);
+ OutStreamer->emitInstruction(
+ MCInstBuilder(RISCV::BEQ)
+ .addReg(RISCV::X6)
+ .addReg(RISCV::X7)
+ .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
+ MCSTI);
+
+ OutStreamer->emitLabel(HandleMismatchSym);
+ }
// | Previous stack frames... |
// +=================================+ <-- [SP + 256]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2dd7240ef941a7..69648d3b2f488d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1932,6 +1932,13 @@ def : Pat<(trap), (UNIMP)>;
// debugger if possible.
def : Pat<(debugtrap), (EBREAK)>;
+let Predicates = [IsRV64], Uses = [X5],
+ Defs = [X1, X6, X7, X28, X29, X30, X31], Size = 8 in
+def HWASAN_CHECK_MEMACCESS
+ : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
+ [(int_hwasan_check_memaccess (i64 X5), GPRJALR:$ptr,
+ (i32 timm:$accessinfo))]>;
+
let Predicates = [IsRV64], Uses = [X5],
Defs = [X1, X6, X7, X28, X29, X30, X31], Size = 8 in
def HWASAN_CHECK_MEMACCESS_SHORTGRANULES
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