[llvm] [HWASAN] Use sign extension in memToShadow() and untagPointer() (PR #103727)

via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 14 02:22:16 PDT 2024


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms

@llvm/pr-subscribers-backend-risc-v

Author: Samuel Holland (SiFiveHolland)

<details>
<summary>Changes</summary>

This allows the shift in untagPointer() to be folded with the shift in memToShadow(), and works for both user and kernel HWASAN. On AArch64, the sequence collapses to a single sbfx instruction, and on RISC-V it avoids consuming a register to hold the shifted mask byte.

This is a backward-compatible change because (for a constant ShadowBase) it only affects the top bits of the pointer returned from memToShadow(), which are ignored by hardware anyway. Note that the AArch64 outline assembly already uses a sbfx instruction for these combined operations.

Additionally use the original tagged pointer to compute the inline tag address, to avoid needing to keep the untagged pointer live.

---

Patch is 393.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/103727.diff


24 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+1-1) 
- (modified) llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (+7-18) 
- (modified) llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll (+1-1) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll (+10-6) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll (+42-36) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll (+4-2) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll (+592-495) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/exception-lifetime.ll (+15-10) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll (+12-8) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll (+4-2) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll (+2-1) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll (+37-26) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll (+74-60) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll (+16-10) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll (+8-5) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll (+8-5) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll (+42-36) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/basic.ll (+337-307) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll (+13-9) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll (+8-5) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/kernel.ll (+3-2) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll (+56-35) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll (+8-5) 
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll (+252-176) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 93677433c04405..005e67f05bce50 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -658,7 +658,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
     OutStreamer->emitInstruction(
         MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),
         MCSTI);
-    OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)
+    OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRAI)
                                      .addReg(RISCV::X6)
                                      .addReg(RISCV::X6)
                                      .addImm(12),
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 95433a216b168d..6495bd76af1834 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -307,7 +307,6 @@ class HWAddressSanitizer {
   struct ShadowTagCheckInfo {
     Instruction *TagMismatchTerm = nullptr;
     Value *PtrLong = nullptr;
-    Value *AddrLong = nullptr;
     Value *PtrTag = nullptr;
     Value *MemTag = nullptr;
   };
@@ -896,7 +895,7 @@ void HWAddressSanitizer::untagPointerOperand(Instruction *I, Value *Addr) {
 
 Value *HWAddressSanitizer::memToShadow(Value *Mem, IRBuilder<> &IRB) {
   // Mem >> Scale
-  Value *Shadow = IRB.CreateLShr(Mem, Mapping.Scale);
+  Value *Shadow = IRB.CreateAShr(Mem, Mapping.Scale);
   if (Mapping.Offset == 0)
     return IRB.CreateIntToPtr(Shadow, PtrTy);
   // (Mem >> Scale) + Offset
@@ -923,8 +922,8 @@ HWAddressSanitizer::insertShadowTagCheck(Value *Ptr, Instruction *InsertBefore,
   R.PtrLong = IRB.CreatePointerCast(Ptr, IntptrTy);
   R.PtrTag =
       IRB.CreateTrunc(IRB.CreateLShr(R.PtrLong, PointerTagShift), Int8Ty);
-  R.AddrLong = untagPointer(IRB, R.PtrLong);
-  Value *Shadow = memToShadow(R.AddrLong, IRB);
+  Value *AddrLong = untagPointer(IRB, R.PtrLong);
+  Value *Shadow = memToShadow(AddrLong, IRB);
   R.MemTag = IRB.CreateLoad(Int8Ty, Shadow);
   Value *TagMismatch = IRB.CreateICmpNE(R.PtrTag, R.MemTag);
 
@@ -1011,7 +1010,7 @@ void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite,
                             LI, CheckFailTerm->getParent());
 
   IRB.SetInsertPoint(TCI.TagMismatchTerm);
-  Value *InlineTagAddr = IRB.CreateOr(TCI.AddrLong, 15);
+  Value *InlineTagAddr = IRB.CreateOr(TCI.PtrLong, 15);
   InlineTagAddr = IRB.CreateIntToPtr(InlineTagAddr, PtrTy);
   Value *InlineTag = IRB.CreateLoad(Int8Ty, InlineTagAddr);
   Value *InlineTagMismatch = IRB.CreateICmpNE(TCI.PtrTag, InlineTag);
@@ -1255,20 +1254,10 @@ Value *HWAddressSanitizer::tagPointer(IRBuilder<> &IRB, Type *Ty,
 
 // Remove tag from an address.
 Value *HWAddressSanitizer::untagPointer(IRBuilder<> &IRB, Value *PtrLong) {
+  unsigned SignExtShift = 64 - PointerTagShift;
   assert(!UsePageAliases);
-  Value *UntaggedPtrLong;
-  if (CompileKernel) {
-    // Kernel addresses have 0xFF in the most significant byte.
-    UntaggedPtrLong =
-        IRB.CreateOr(PtrLong, ConstantInt::get(PtrLong->getType(),
-                                               TagMaskByte << PointerTagShift));
-  } else {
-    // Userspace addresses have 0x00.
-    UntaggedPtrLong = IRB.CreateAnd(
-        PtrLong, ConstantInt::get(PtrLong->getType(),
-                                  ~(TagMaskByte << PointerTagShift)));
-  }
-  return UntaggedPtrLong;
+
+  return IRB.CreateAShr(IRB.CreateShl(PtrLong, SignExtShift), SignExtShift);
 }
 
 Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB) {
diff --git a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
index 12c95206d21bed..8a8e73967e78c6 100644
--- a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
+++ b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
@@ -26,7 +26,7 @@ declare void @llvm.hwasan.check.memaccess.shortgranules(ptr, ptr, i32)
 ; CHECK-NEXT: .hidden __hwasan_check_x10_2_short
 ; CHECK-NEXT: __hwasan_check_x10_2_short:
 ; CHECK-NEXT: slli    t1, a0, 8
-; CHECK-NEXT: srli    t1, t1, 12
+; CHECK-NEXT: srai    t1, t1, 12
 ; CHECK-NEXT: add     t1, t0, t1
 ; CHECK-NEXT: lbu     t1, 0(t1)
 ; CHECK-NEXT: srli    t2, a0, 56
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll
index bbfb35549b5b61..f9105010db68bd 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll
@@ -13,7 +13,8 @@ define void @test_alloca() sanitize_hwaddress {
 ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
+; CHECK-NEXT:    [[TMP23:%.*]] = shl i64 [[TMP0]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i64 [[TMP23]], 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
 ; CHECK-NEXT:    [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
 ; CHECK-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
@@ -35,14 +36,16 @@ define void @test_alloca() sanitize_hwaddress {
 ; CHECK-NEXT:    [[TMP15:%.*]] = call i8 @__hwasan_generate_tag()
 ; CHECK-NEXT:    [[TMP16:%.*]] = zext i8 [[TMP15]] to i64
 ; CHECK-NEXT:    [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64
-; CHECK-NEXT:    [[TMP18:%.*]] = and i64 [[TMP17]], 72057594037927935
+; CHECK-NEXT:    [[TMP30:%.*]] = shl i64 [[TMP17]], 8
+; CHECK-NEXT:    [[TMP18:%.*]] = ashr i64 [[TMP30]], 8
 ; CHECK-NEXT:    [[TMP19:%.*]] = shl i64 [[TMP16]], 56
 ; CHECK-NEXT:    [[TMP20:%.*]] = or i64 [[TMP18]], [[TMP19]]
 ; CHECK-NEXT:    [[X_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr
 ; CHECK-NEXT:    [[TMP21:%.*]] = trunc i64 [[TMP16]] to i8
 ; CHECK-NEXT:    [[TMP22:%.*]] = ptrtoint ptr [[X]] to i64
-; CHECK-NEXT:    [[TMP23:%.*]] = and i64 [[TMP22]], 72057594037927935
-; CHECK-NEXT:    [[TMP24:%.*]] = lshr i64 [[TMP23]], 4
+; CHECK-NEXT:    [[TMP35:%.*]] = shl i64 [[TMP22]], 8
+; CHECK-NEXT:    [[TMP36:%.*]] = ashr i64 [[TMP35]], 8
+; CHECK-NEXT:    [[TMP24:%.*]] = ashr i64 [[TMP36]], 4
 ; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP24]]
 ; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr i8, ptr [[TMP25]], i32 0
 ; CHECK-NEXT:    store i8 4, ptr [[TMP26]], align 1
@@ -51,8 +54,9 @@ define void @test_alloca() sanitize_hwaddress {
 ; CHECK-NEXT:    call void @use32(ptr nonnull [[X_HWASAN]])
 ; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
 ; CHECK-NEXT:    [[TMP29:%.*]] = ptrtoint ptr [[X]] to i64
-; CHECK-NEXT:    [[TMP30:%.*]] = and i64 [[TMP29]], 72057594037927935
-; CHECK-NEXT:    [[TMP31:%.*]] = lshr i64 [[TMP30]], 4
+; CHECK-NEXT:    [[TMP33:%.*]] = shl i64 [[TMP29]], 8
+; CHECK-NEXT:    [[TMP34:%.*]] = ashr i64 [[TMP33]], 8
+; CHECK-NEXT:    [[TMP31:%.*]] = ashr i64 [[TMP34]], 4
 ; CHECK-NEXT:    [[TMP32:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP31]]
 ; CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 [[TMP28]], i64 1, i1 false)
 ; CHECK-NEXT:    ret void
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
index 23b1043c700165..fb39d0984e2d4a 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
@@ -45,26 +45,29 @@ define void @test_alloca() sanitize_hwaddress !dbg !15 {
 ; DYNAMIC-SHADOW-NEXT:      #dbg_value(!DIArgList(ptr [[X]], ptr [[X]]), [[META10:![0-9]+]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref), [[META12:![0-9]+]])
 ; DYNAMIC-SHADOW-NEXT:    [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG13:![0-9]+]]
 ; DYNAMIC-SHADOW-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]], !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP9:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP10:%.*]] = and i64 [[TMP9]], 72057594037927935, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP10]], 4, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP11]], !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP12]], i32 0, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    store i8 4, ptr [[TMP13]], align 1, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG13]]
-; DYNAMIC-SHADOW-NEXT:    store i8 [[TMP8]], ptr [[TMP14]], align 1, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP4]], 8, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP6:%.*]] = ashr i64 [[TMP5]], 8, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP7:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]], !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP10:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP11:%.*]] = shl i64 [[TMP10]], 8, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP12:%.*]] = ashr i64 [[TMP11]], 8, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP13:%.*]] = ashr i64 [[TMP12]], 4, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP13]], !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP14]], i32 0, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    store i8 4, ptr [[TMP17]], align 1, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG13]]
+; DYNAMIC-SHADOW-NEXT:    store i8 [[TMP9]], ptr [[TMP16]], align 1, !dbg [[DBG13]]
 ; DYNAMIC-SHADOW-NEXT:    call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13]]
 ; DYNAMIC-SHADOW-NEXT:    [[TMP15:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP16:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 72057594037927935, !dbg [[DBG14]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP17]], 4, !dbg [[DBG14]]
-; DYNAMIC-SHADOW-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP18]], !dbg [[DBG14]]
-; DYNAMIC-SHADOW-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[TMP19]], i8 [[TMP15]], i64 1, i1 false), !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP19:%.*]] = shl i64 [[TMP18]], 8, !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP20:%.*]] = ashr i64 [[TMP19]], 8, !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP21:%.*]] = ashr i64 [[TMP20]], 4, !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    [[TMP22:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP21]], !dbg [[DBG14]]
+; DYNAMIC-SHADOW-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[TMP22]], i8 [[TMP15]], i64 1, i1 false), !dbg [[DBG14]]
 ; DYNAMIC-SHADOW-NEXT:    ret void, !dbg [[DBG14]]
 ;
 ; ZERO-BASED-SHADOW-LABEL: define void @test_alloca
@@ -80,26 +83,29 @@ define void @test_alloca() sanitize_hwaddress !dbg !15 {
 ; ZERO-BASED-SHADOW-NEXT:      #dbg_value(!DIArgList(ptr [[X]], ptr [[X]]), [[META10:![0-9]+]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref), [[META12:![0-9]+]])
 ; ZERO-BASED-SHADOW-NEXT:    [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG13:![0-9]+]]
 ; ZERO-BASED-SHADOW-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]], !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP9:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP10:%.*]] = and i64 [[TMP9]], 72057594037927935, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP11:%.*]] = lshr i64 [[TMP10]], 4, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP12]], i32 0, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    store i8 4, ptr [[TMP13]], align 1, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG13]]
-; ZERO-BASED-SHADOW-NEXT:    store i8 [[TMP8]], ptr [[TMP14]], align 1, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP4]], 8, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP6:%.*]] = ashr i64 [[TMP5]], 8, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP7:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]], !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP10:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP11:%.*]] = shl i64 [[TMP10]], 8, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP12:%.*]] = ashr i64 [[TMP11]], 8, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP13:%.*]] = ashr i64 [[TMP12]], 4, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP14]], i32 0, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    store i8 4, ptr [[TMP17]], align 1, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG13]]
+; ZERO-BASED-SHADOW-NEXT:    store i8 [[TMP9]], ptr [[TMP16]], align 1, !dbg [[DBG13]]
 ; ZERO-BASED-SHADOW-NEXT:    call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13]]
 ; ZERO-BASED-SHADOW-NEXT:    [[TMP15:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP16:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 72057594037927935, !dbg [[DBG14]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP18:%.*]] = lshr i64 [[TMP17]], 4, !dbg [[DBG14]]
-; ZERO-BASED-SHADOW-NEXT:    [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr, !dbg [[DBG14]]
-; ZERO-BASED-SHADOW-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[TMP19]], i8 [[TMP15]], i64 1, i1 false), !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP19:%.*]] = shl i64 [[TMP18]], 8, !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP20:%.*]] = ashr i64 [[TMP19]], 8, !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP21:%.*]] = ashr i64 [[TMP20]], 4, !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr, !dbg [[DBG14]]
+; ZERO-BASED-SHADOW-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[TMP22]], i8 [[TMP15]], i64 1, i1 false), !dbg [[DBG14]]
 ; ZERO-BASED-SHADOW-NEXT:    ret void, !dbg [[DBG14]]
 ;
 entry:
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll
index 152d1bfd3288d1..008cecc1d3ef87 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll
@@ -11,7 +11,8 @@ define void @atomicrmw(ptr %ptr) sanitize_hwaddress {
 ; CHECK-SAME: (ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP0]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i64 [[TMP5]], 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
 ; CHECK-NEXT:    [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
@@ -30,7 +31,8 @@ define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddre
 ; CHECK-SAME: (ptr [[PTR:%.*]], i64 [[COMPARE_TO:%.*]], i64 [[NEW_VALUE:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP0]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i64 [[TMP5]], 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
 ; CHECK-NEXT:    [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
index 9cebe2e845f772..45c6630d69b849 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
@@ -9,8 +9,6 @@
 ; RUN: opt < %s -passes=hwasan -hwasan-recover=0 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=ABORT-ZERO-BASED-SHADOW
 ; RUN: opt < %s -passes=hwasan -hwasan-recover=1 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=RECOVER-ZERO-BASED-SHADOW
 
-; CHECK: @llvm.used = appending global [1 x ptr] [ptr @hwasan.module_ctor]
-; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @hwasan.module_ctor, ptr @hwasan.module_ctor }]
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "riscv64-unknown-linux"
@@ -20,23 +18,25 @@ define i8 @test_load8(ptr %a) sanitize_hwaddress {
 ; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
+; CHECK-NEXT:    [[TMP7:%.*]] = shl i64 [[TMP0]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i64 [[TMP7]], 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
 ; CHECK-NEXT:    [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
 ; CHECK-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
 ; CHECK-NEXT:    [[TMP5:%.*]] = lshr i64 [[TMP4]], 56
 ; CHECK-NEXT:    [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
-; CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP4]], 72057594037927935
-; CHECK-NEXT:    [[TMP8:%.*]] = lshr i64 [[TMP7]], 4
+; CHECK-NEXT:    [[TMP14:%.*]] = shl i64 [[TMP4]], 8
+; CHECK-NEXT:    [[TMP15:%.*]] = ashr i64 [[TMP14]], 8
+; CHECK-NEXT:    [[TMP8:%.*]] = ashr i64 [[TMP15]], 4
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[TMP8]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
 ; CHECK-NEXT:    [[TMP11:%.*]] = icmp ne i8 [[TMP6]], [[TMP10]]
 ; CHECK-NEXT:    br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1:![0-9]+]]
-; CHECK:       12:
+; CHECK:       14:
 ; CHECK-NEXT:    call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP3]], ptr [[A]], i32 0)
 ; CHECK-NEXT:    br label [[TMP13]]
-; CHECK:       13:
+; CHECK:       15:
 ; CHECK-NEXT:    [[B:%.*]] = load i8, ptr [[A]], align 4
 ; CHECK-NEXT:    re...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/103727


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