[llvm] 5ab99bf - [RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 14 01:42:35 PDT 2024
Author: Anton Sidorenko
Date: 2024-08-14T11:42:31+03:00
New Revision: 5ab99bf1a757c5ad7115280f374d9af4f1b98bc9
URL: https://github.com/llvm/llvm-project/commit/5ab99bf1a757c5ad7115280f374d9af4f1b98bc9
DIFF: https://github.com/llvm/llvm-project/commit/5ab99bf1a757c5ad7115280f374d9af4f1b98bc9.diff
LOG: [RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)
Syntacore SCR4 is a microcontroller-class processor core that has much
in common with SCR3, but also supports F and D extensions.
Overview: https://syntacore.com/products/scr4
Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core which scheduling model almost match SCR4.
Overview: https://syntacore.com/products/scr5
Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>
Added:
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-ALU.s
llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-LSU.s
llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s
Modified:
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVProcessors.td
Removed:
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s
llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index d96fafbe608077..c58ebeeafe13f5 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -51,7 +51,7 @@ include "RISCVSchedSiFive7.td"
include "RISCVSchedSiFiveP400.td"
include "RISCVSchedSiFiveP600.td"
include "RISCVSchedSyntacoreSCR1.td"
-include "RISCVSchedSyntacoreSCR3.td"
+include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedXiangShanNanHu.td"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 8ba649614a19c0..640fe9670d542b 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -333,7 +333,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
- NoSchedModel,
+ SyntacoreSCR4RV32Model,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
@@ -345,7 +345,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
- NoSchedModel,
+ SyntacoreSCR4RV64Model,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
@@ -358,7 +358,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
- NoSchedModel,
+ SyntacoreSCR5RV32Model,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
@@ -371,7 +371,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
- NoSchedModel,
+ SyntacoreSCR5RV64Model,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
deleted file mode 100644
index 607637bc0de596..00000000000000
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
+++ /dev/null
@@ -1,189 +0,0 @@
-//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- tablegen -*-=//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-
-// This model covers SYNTACORE_SCR3_RV32IMC and SYNTACORE_RV64IMAC
-// configurations (syntacore-scr3-rv32/64).
-// Overview: https://syntacore.com/products/scr3
-
-// SCR3 is single-issue in-order processor
-class SyntacoreSCR3Model : SchedMachineModel {
- let MicroOpBufferSize = 0;
- let IssueWidth = 1;
- let LoadLatency = 2;
- let MispredictPenalty = 3;
- let CompleteModel = 0;
- let UnsupportedFeatures = [HasStdExtD, HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
- HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
- HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
- HasVInstructions];
-}
-
-// Branching
-multiclass SCR3_Branching<ProcResourceKind BRU> {
- def : WriteRes<WriteJmp, [BRU]>;
- def : WriteRes<WriteJal, [BRU]>;
- def : WriteRes<WriteJalr, [BRU]>;
-}
-
-// Single-cycle integer arithmetic and logic
-multiclass SCR3_IntALU<ProcResourceKind ALU> {
- def : WriteRes<WriteIALU, [ALU]>;
- def : WriteRes<WriteIALU32, [ALU]>;
- def : WriteRes<WriteShiftImm, [ALU]>;
- def : WriteRes<WriteShiftImm32, [ALU]>;
- def : WriteRes<WriteShiftReg, [ALU]>;
- def : WriteRes<WriteShiftReg32, [ALU]>;
-}
-
-// Integer multiplication
-multiclass SCR3_IntMul<ProcResourceKind MUL> {
- let Latency = 2 in {
- def : WriteRes<WriteIMul, [MUL]>;
- def : WriteRes<WriteIMul32, [MUL]>;
- }
-}
-
-// Integer division
-multiclass SCR3_IntDiv<ProcResourceKind DIV, int DivLatency> {
- let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in {
- def : WriteRes<WriteIDiv, [DIV]>;
- def : WriteRes<WriteIDiv32, [DIV]>;
- def : WriteRes<WriteIRem, [DIV]>;
- def : WriteRes<WriteIRem32, [DIV]>;
- }
-}
-
-// Load/store instructions on SCR3 have latency 2
-multiclass SCR3_Memory<ProcResourceKind LSU> {
- let Latency = 2 in {
- def : WriteRes<WriteSTB, [LSU]>;
- def : WriteRes<WriteSTH, [LSU]>;
- def : WriteRes<WriteSTW, [LSU]>;
- def : WriteRes<WriteSTD, [LSU]>;
- def : WriteRes<WriteLDB, [LSU]>;
- def : WriteRes<WriteLDH, [LSU]>;
- def : WriteRes<WriteLDW, [LSU]>;
- def : WriteRes<WriteLDD, [LSU]>;
- }
-}
-
-// Atomic memory
-multiclass SCR3_AtomicMemory<ProcResourceKind LSU> {
- let Latency = 20 in {
- def : WriteRes<WriteAtomicLDW, [LSU]>;
- def : WriteRes<WriteAtomicLDD, [LSU]>;
- def : WriteRes<WriteAtomicW, [LSU]>;
- def : WriteRes<WriteAtomicD, [LSU]>;
- def : WriteRes<WriteAtomicSTW, [LSU]>;
- def : WriteRes<WriteAtomicSTD, [LSU]>;
- }
-}
-
-// Others
-multiclass SCR3_Other {
- def : WriteRes<WriteCSR, []>;
- def : WriteRes<WriteNop, []>;
-
- def : InstRW<[WriteIALU], (instrs COPY)>;
-}
-
-
-multiclass SCR3_Unsupported {
- defm : UnsupportedSchedD;
- defm : UnsupportedSchedF;
- defm : UnsupportedSchedSFB;
- defm : UnsupportedSchedV;
- defm : UnsupportedSchedXsfvcp;
- defm : UnsupportedSchedZabha;
- defm : UnsupportedSchedZba;
- defm : UnsupportedSchedZbb;
- defm : UnsupportedSchedZbc;
- defm : UnsupportedSchedZbs;
- defm : UnsupportedSchedZbkb;
- defm : UnsupportedSchedZbkx;
- defm : UnsupportedSchedZfa;
- defm : UnsupportedSchedZfh;
- defm : UnsupportedSchedZvk;
-}
-
-// Bypasses (none)
-multiclass SCR3_NoReadAdvances {
- def : ReadAdvance<ReadJmp, 0>;
- def : ReadAdvance<ReadJalr, 0>;
- def : ReadAdvance<ReadCSR, 0>;
- def : ReadAdvance<ReadStoreData, 0>;
- def : ReadAdvance<ReadMemBase, 0>;
- def : ReadAdvance<ReadIALU, 0>;
- def : ReadAdvance<ReadIALU32, 0>;
- def : ReadAdvance<ReadShiftImm, 0>;
- def : ReadAdvance<ReadShiftImm32, 0>;
- def : ReadAdvance<ReadShiftReg, 0>;
- def : ReadAdvance<ReadShiftReg32, 0>;
- def : ReadAdvance<ReadIDiv, 0>;
- def : ReadAdvance<ReadIDiv32, 0>;
- def : ReadAdvance<ReadIRem, 0>;
- def : ReadAdvance<ReadIRem32, 0>;
- def : ReadAdvance<ReadIMul, 0>;
- def : ReadAdvance<ReadIMul32, 0>;
- def : ReadAdvance<ReadAtomicWA, 0>;
- def : ReadAdvance<ReadAtomicWD, 0>;
- def : ReadAdvance<ReadAtomicDA, 0>;
- def : ReadAdvance<ReadAtomicDD, 0>;
- def : ReadAdvance<ReadAtomicLDW, 0>;
- def : ReadAdvance<ReadAtomicLDD, 0>;
- def : ReadAdvance<ReadAtomicSTW, 0>;
- def : ReadAdvance<ReadAtomicSTD, 0>;
-}
-
-def SyntacoreSCR3RV32Model : SyntacoreSCR3Model;
-
-let SchedModel = SyntacoreSCR3RV32Model in {
- let BufferSize = 0 in {
- def SCR3RV32_ALU : ProcResource<1>;
- def SCR3RV32_MUL : ProcResource<1>;
- def SCR3RV32_DIV : ProcResource<1>;
- def SCR3RV32_LSU : ProcResource<1>;
- def SCR3RV32_CFU : ProcResource<1>;
- }
-
- defm : SCR3_Branching<SCR3RV32_CFU>;
- defm : SCR3_IntALU<SCR3RV32_ALU>;
- defm : SCR3_IntMul<SCR3RV32_MUL>;
- defm : SCR3_IntDiv<SCR3RV32_DIV, /* div latency = */ 8>;
- defm : SCR3_Memory<SCR3RV32_LSU>;
- defm : SCR3_AtomicMemory<SCR3RV32_LSU>;
- defm : SCR3_Other;
-
- defm : SCR3_Unsupported;
- defm : SCR3_NoReadAdvances;
-}
-
-def SyntacoreSCR3RV64Model : SyntacoreSCR3Model;
-
-let SchedModel = SyntacoreSCR3RV64Model in {
- let BufferSize = 0 in {
- def SCR3RV64_ALU : ProcResource<1>;
- def SCR3RV64_MUL : ProcResource<1>;
- def SCR3RV64_DIV : ProcResource<1>;
- def SCR3RV64_LSU : ProcResource<1>;
- def SCR3RV64_CFU : ProcResource<1>;
- }
-
- defm : SCR3_Branching<SCR3RV64_CFU>;
- defm : SCR3_IntALU<SCR3RV64_ALU>;
- defm : SCR3_IntMul<SCR3RV64_MUL>;
- defm : SCR3_IntDiv<SCR3RV64_DIV, /* div latency = */ 11>;
- defm : SCR3_Memory<SCR3RV64_LSU>;
- defm : SCR3_AtomicMemory<SCR3RV64_LSU>;
- defm : SCR3_Other;
-
- defm : SCR3_Unsupported;
- defm : SCR3_NoReadAdvances;
-}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
new file mode 100644
index 00000000000000..a1c63f22e5c090
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
@@ -0,0 +1,451 @@
+//==- RISCVSchedSyntacoreSCR345.td - SCR3/4/5 Sched Defs -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// This file covers scheduling models for Syntacore SCR3, SCR4 and SCR5
+// processors.
+// Configurations:
+// * SCR3 rv32imc and rv64imac, overview https://syntacore.com/products/scr3
+// * SCR4 rv32imfdc and rv64imafdc, overview https://syntacore.com/products/scr4
+// * SCR5 rv32imafdc and rv64imafdc, overview
+// https://syntacore.com/products/scr5
+
+// SCR3-5 are single-issue in-order processors
+class SyntacoreSchedModel : SchedMachineModel {
+ let MicroOpBufferSize = 0;
+ let IssueWidth = 1;
+ let MispredictPenalty = 3;
+ let CompleteModel = 0;
+ let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+// Branching
+multiclass SCR_Branching<ProcResourceKind BRU> {
+ def : WriteRes<WriteJmp, [BRU]>;
+ def : WriteRes<WriteJal, [BRU]>;
+ def : WriteRes<WriteJalr, [BRU]>;
+}
+
+// Single-cycle integer arithmetic and logic
+multiclass SCR_IntALU<ProcResourceKind ALU> {
+ def : WriteRes<WriteIALU, [ALU]>;
+ def : WriteRes<WriteIALU32, [ALU]>;
+ def : WriteRes<WriteShiftImm, [ALU]>;
+ def : WriteRes<WriteShiftImm32, [ALU]>;
+ def : WriteRes<WriteShiftReg, [ALU]>;
+ def : WriteRes<WriteShiftReg32, [ALU]>;
+}
+
+// Integer multiplication
+multiclass SCR_IntMul<ProcResourceKind MUL> {
+ let Latency = 2 in {
+ def : WriteRes<WriteIMul, [MUL]>;
+ def : WriteRes<WriteIMul32, [MUL]>;
+ }
+}
+
+// Integer division
+multiclass SCR_IntDiv<ProcResourceKind DIV, int DivLatency> {
+ let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in {
+ def : WriteRes<WriteIDiv, [DIV]>;
+ def : WriteRes<WriteIDiv32, [DIV]>;
+ def : WriteRes<WriteIRem, [DIV]>;
+ def : WriteRes<WriteIRem32, [DIV]>;
+ }
+}
+
+// Load/store instructions
+multiclass SCR_BasicMemory<ProcResourceKind LSU, int LoadStoreLatency> {
+ let Latency = LoadStoreLatency in {
+ def : WriteRes<WriteSTB, [LSU]>;
+ def : WriteRes<WriteSTH, [LSU]>;
+ def : WriteRes<WriteSTW, [LSU]>;
+ def : WriteRes<WriteSTD, [LSU]>;
+ def : WriteRes<WriteLDB, [LSU]>;
+ def : WriteRes<WriteLDH, [LSU]>;
+ def : WriteRes<WriteLDW, [LSU]>;
+ def : WriteRes<WriteLDD, [LSU]>;
+ }
+}
+
+// Floating-point load/store instructions
+multiclass SCR_FPMemory<ProcResourceKind LSU, int FPLoadStoreLatency> {
+ let Latency = FPLoadStoreLatency in {
+ def : WriteRes<WriteFST32, [LSU]>;
+ def : WriteRes<WriteFST64, [LSU]>;
+ def : WriteRes<WriteFLD32, [LSU]>;
+ def : WriteRes<WriteFLD64, [LSU]>;
+ }
+}
+
+// Atomic memory
+multiclass SCR_AtomicMemory<ProcResourceKind LSU> {
+ let Latency = 20 in {
+ def : WriteRes<WriteAtomicLDW, [LSU]>;
+ def : WriteRes<WriteAtomicLDD, [LSU]>;
+ def : WriteRes<WriteAtomicW, [LSU]>;
+ def : WriteRes<WriteAtomicD, [LSU]>;
+ def : WriteRes<WriteAtomicSTW, [LSU]>;
+ def : WriteRes<WriteAtomicSTD, [LSU]>;
+ }
+}
+
+// Floating-point unit (without division and SQRT)
+multiclass SCR_FPU<ProcResourceKind FPU> {
+ // Single and double-precision computational instructions
+ def : WriteRes<WriteFAdd32, [FPU]> { let Latency = 3; }
+ def : WriteRes<WriteFAdd64, [FPU]> { let Latency = 3; }
+ def : WriteRes<WriteFMul32, [FPU]> { let Latency = 4; }
+ def : WriteRes<WriteFMul64, [FPU]> { let Latency = 4; }
+ def : WriteRes<WriteFMA32, [FPU]> { let Latency = 4; }
+ def : WriteRes<WriteFMA64, [FPU]> { let Latency = 4; }
+ def : WriteRes<WriteFSGNJ32, [FPU]> { let Latency = 2; }
+ def : WriteRes<WriteFSGNJ64, [FPU]> { let Latency = 2; }
+ def : WriteRes<WriteFMinMax32, [FPU]> { let Latency = 2; }
+ def : WriteRes<WriteFMinMax64, [FPU]> { let Latency = 2; }
+
+ // Conversion and move instructions
+ let Latency = 3 in {
+ def : WriteRes<WriteFCvtI32ToF32, [FPU]>;
+ def : WriteRes<WriteFCvtI32ToF64, [FPU]>;
+ def : WriteRes<WriteFCvtI64ToF32, [FPU]>;
+ def : WriteRes<WriteFCvtI64ToF64, [FPU]>;
+ def : WriteRes<WriteFCvtF32ToF64, [FPU]>;
+ def : WriteRes<WriteFCvtF64ToF32, [FPU]>;
+ }
+
+ let Latency = 2 in {
+ def : WriteRes<WriteFCvtF32ToI32, [FPU]>;
+ def : WriteRes<WriteFCvtF64ToI32, [FPU]>;
+ def : WriteRes<WriteFCvtF32ToI64, [FPU]>;
+ def : WriteRes<WriteFCvtF64ToI64, [FPU]>;
+ }
+
+ let Latency = 2 in {
+ def : WriteRes<WriteFMovI32ToF32, [FPU]>;
+ def : WriteRes<WriteFMovF32ToI32, [FPU]>;
+ def : WriteRes<WriteFMovI64ToF64, [FPU]>;
+ def : WriteRes<WriteFMovF64ToI64, [FPU]>;
+ }
+
+ let Latency = 2 in {
+ def : WriteRes<WriteFClass32, [FPU]>;
+ def : WriteRes<WriteFClass64, [FPU]>;
+ }
+
+ // Comparisons
+ let Latency = 2 in {
+ def : WriteRes<WriteFCmp32, [FPU]>;
+ def : WriteRes<WriteFCmp64, [FPU]>;
+ }
+}
+
+// FP division and SQRT is not pipelined
+multiclass SCR_FDU<ProcResourceKind FDU> {
+ def : WriteRes<WriteFDiv32, [FDU]> {
+ let Latency = 10;
+ let ReleaseAtCycles = [8];
+ }
+ def : WriteRes<WriteFDiv64, [FDU]> {
+ let Latency = 17;
+ let ReleaseAtCycles = [15];
+ }
+
+ def : WriteRes<WriteFSqrt32, [FDU]> {
+ let Latency = 19;
+ let ReleaseAtCycles = [19];
+ }
+ def : WriteRes<WriteFSqrt64, [FDU]> {
+ let Latency = 33;
+ let ReleaseAtCycles = [33];
+ }
+}
+
+// Others
+multiclass SCR_Other {
+ def : WriteRes<WriteCSR, []>;
+ def : WriteRes<WriteNop, []>;
+
+ def : InstRW<[WriteIALU], (instrs COPY)>;
+}
+
+// Unsupported scheduling classes for SCR3-5.
+multiclass SCR_Unsupported {
+ defm : UnsupportedSchedSFB;
+ defm : UnsupportedSchedV;
+ defm : UnsupportedSchedXsfvcp;
+ defm : UnsupportedSchedZabha;
+ defm : UnsupportedSchedZba;
+ defm : UnsupportedSchedZbb;
+ defm : UnsupportedSchedZbc;
+ defm : UnsupportedSchedZbs;
+ defm : UnsupportedSchedZbkb;
+ defm : UnsupportedSchedZbkx;
+ defm : UnsupportedSchedZfa;
+ defm : UnsupportedSchedZfh;
+ defm : UnsupportedSchedZvk;
+}
+
+multiclass SCR3_Unsupported {
+ defm : SCR_Unsupported;
+ defm : UnsupportedSchedD;
+ defm : UnsupportedSchedF;
+}
+
+// Bypasses (none)
+multiclass SCR_NoReadAdvances {
+ def : ReadAdvance<ReadJmp, 0>;
+ def : ReadAdvance<ReadJalr, 0>;
+ def : ReadAdvance<ReadCSR, 0>;
+ def : ReadAdvance<ReadStoreData, 0>;
+ def : ReadAdvance<ReadMemBase, 0>;
+ def : ReadAdvance<ReadIALU, 0>;
+ def : ReadAdvance<ReadIALU32, 0>;
+ def : ReadAdvance<ReadShiftImm, 0>;
+ def : ReadAdvance<ReadShiftImm32, 0>;
+ def : ReadAdvance<ReadShiftReg, 0>;
+ def : ReadAdvance<ReadShiftReg32, 0>;
+ def : ReadAdvance<ReadIDiv, 0>;
+ def : ReadAdvance<ReadIDiv32, 0>;
+ def : ReadAdvance<ReadIRem, 0>;
+ def : ReadAdvance<ReadIRem32, 0>;
+ def : ReadAdvance<ReadIMul, 0>;
+ def : ReadAdvance<ReadIMul32, 0>;
+ def : ReadAdvance<ReadAtomicWA, 0>;
+ def : ReadAdvance<ReadAtomicWD, 0>;
+ def : ReadAdvance<ReadAtomicDA, 0>;
+ def : ReadAdvance<ReadAtomicDD, 0>;
+ def : ReadAdvance<ReadAtomicLDW, 0>;
+ def : ReadAdvance<ReadAtomicLDD, 0>;
+ def : ReadAdvance<ReadAtomicSTW, 0>;
+ def : ReadAdvance<ReadAtomicSTD, 0>;
+}
+
+// Floating-point bypasses (none)
+multiclass SCR4_SCR5_NoReadAdvances {
+ defm : SCR_NoReadAdvances;
+ def : ReadAdvance<ReadFStoreData, 0>;
+ def : ReadAdvance<ReadFMemBase, 0>;
+ def : ReadAdvance<ReadFAdd32, 0>;
+ def : ReadAdvance<ReadFAdd64, 0>;
+ def : ReadAdvance<ReadFMul32, 0>;
+ def : ReadAdvance<ReadFMul64, 0>;
+ def : ReadAdvance<ReadFMA32, 0>;
+ def : ReadAdvance<ReadFMA32Addend, 0>;
+ def : ReadAdvance<ReadFMA64, 0>;
+ def : ReadAdvance<ReadFMA64Addend, 0>;
+ def : ReadAdvance<ReadFDiv32, 0>;
+ def : ReadAdvance<ReadFDiv64, 0>;
+ def : ReadAdvance<ReadFSqrt32, 0>;
+ def : ReadAdvance<ReadFSqrt64, 0>;
+ def : ReadAdvance<ReadFCmp32, 0>;
+ def : ReadAdvance<ReadFCmp64, 0>;
+ def : ReadAdvance<ReadFSGNJ32, 0>;
+ def : ReadAdvance<ReadFSGNJ64, 0>;
+ def : ReadAdvance<ReadFMinMax32, 0>;
+ def : ReadAdvance<ReadFMinMax64, 0>;
+ def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+ def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+ def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+ def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+ def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+ def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+ def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+ def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+ def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+ def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+ def : ReadAdvance<ReadFMovF32ToI32, 0>;
+ def : ReadAdvance<ReadFMovI32ToF32, 0>;
+ def : ReadAdvance<ReadFMovF64ToI64, 0>;
+ def : ReadAdvance<ReadFMovI64ToF64, 0>;
+ def : ReadAdvance<ReadFClass32, 0>;
+ def : ReadAdvance<ReadFClass64, 0>;
+}
+
+//===----------------------------------------------------------------------===//
+// SCR3 scheduling model definition
+
+def SyntacoreSCR3RV32Model : SyntacoreSchedModel {
+ let LoadLatency = 2;
+}
+
+let SchedModel = SyntacoreSCR3RV32Model in {
+ let BufferSize = 0 in {
+ def SCR3RV32_ALU : ProcResource<1>;
+ def SCR3RV32_MUL : ProcResource<1>;
+ def SCR3RV32_DIV : ProcResource<1>;
+ def SCR3RV32_LSU : ProcResource<1>;
+ def SCR3RV32_CFU : ProcResource<1>;
+ }
+
+ defm : SCR_Branching<SCR3RV32_CFU>;
+ defm : SCR_IntALU<SCR3RV32_ALU>;
+ defm : SCR_IntMul<SCR3RV32_MUL>;
+ defm : SCR_IntDiv<SCR3RV32_DIV, /* div latency = */ 8>;
+ defm : SCR_BasicMemory<SCR3RV32_LSU, /* load & store latency = */ 2>;
+ defm : SCR_AtomicMemory<SCR3RV32_LSU>;
+ defm : SCR_Other;
+
+ defm : SCR3_Unsupported;
+ defm : SCR_NoReadAdvances;
+}
+
+def SyntacoreSCR3RV64Model : SyntacoreSchedModel {
+ let LoadLatency = 2;
+}
+
+let SchedModel = SyntacoreSCR3RV64Model in {
+ let BufferSize = 0 in {
+ def SCR3RV64_ALU : ProcResource<1>;
+ def SCR3RV64_MUL : ProcResource<1>;
+ def SCR3RV64_DIV : ProcResource<1>;
+ def SCR3RV64_LSU : ProcResource<1>;
+ def SCR3RV64_CFU : ProcResource<1>;
+ }
+
+ defm : SCR_Branching<SCR3RV64_CFU>;
+ defm : SCR_IntALU<SCR3RV64_ALU>;
+ defm : SCR_IntMul<SCR3RV64_MUL>;
+ defm : SCR_IntDiv<SCR3RV64_DIV, /* div latency = */ 11>;
+ defm : SCR_BasicMemory<SCR3RV64_LSU, /* load & store latency = */ 2>;
+ defm : SCR_AtomicMemory<SCR3RV64_LSU>;
+ defm : SCR_Other;
+
+ defm : SCR3_Unsupported;
+ defm : SCR_NoReadAdvances;
+}
+
+//===----------------------------------------------------------------------===//
+// SCR4 scheduling model definition
+
+def SyntacoreSCR4RV32Model : SyntacoreSchedModel {
+ let LoadLatency = 2;
+}
+
+let SchedModel = SyntacoreSCR4RV32Model in {
+ let BufferSize = 0 in {
+ def SCR4RV32_ALU : ProcResource<1>;
+ def SCR4RV32_MUL : ProcResource<1>;
+ def SCR4RV32_DIV : ProcResource<1>;
+ def SCR4RV32_LSU : ProcResource<1>;
+ def SCR4RV32_CFU : ProcResource<1>;
+ def SCR4RV32_FPU : ProcResource<1>;
+ def SCR4RV32_FDU : ProcResource<1>; // FP div and sqrt resource
+ }
+
+ defm : SCR_Branching<SCR4RV32_CFU>;
+ defm : SCR_IntALU<SCR4RV32_ALU>;
+ defm : SCR_IntMul<SCR4RV32_MUL>;
+ defm : SCR_IntDiv<SCR4RV32_DIV, /* div latency = */ 8>;
+ defm : SCR_BasicMemory<SCR4RV32_LSU, /* load & store latency = */ 2>;
+ defm : SCR_FPMemory<SCR4RV32_LSU, /* load & store latency = */ 2>;
+ defm : SCR_AtomicMemory<SCR4RV32_LSU>;
+ defm : SCR_FPU<SCR4RV32_FPU>;
+ defm : SCR_FDU<SCR4RV32_FDU>;
+ defm : SCR_Other;
+
+ defm : SCR_Unsupported;
+ defm : SCR4_SCR5_NoReadAdvances;
+}
+
+def SyntacoreSCR4RV64Model : SyntacoreSchedModel {
+ let LoadLatency = 2;
+}
+
+let SchedModel = SyntacoreSCR4RV64Model in {
+ let BufferSize = 0 in {
+ def SCR4RV64_ALU : ProcResource<1>;
+ def SCR4RV64_MUL : ProcResource<1>;
+ def SCR4RV64_DIV : ProcResource<1>;
+ def SCR4RV64_LSU : ProcResource<1>;
+ def SCR4RV64_CFU : ProcResource<1>;
+ def SCR4RV64_FPU : ProcResource<1>;
+ def SCR4RV64_FDU : ProcResource<1>; // FP div and sqrt resource
+ }
+
+ defm : SCR_Branching<SCR4RV64_CFU>;
+ defm : SCR_IntALU<SCR4RV64_ALU>;
+ defm : SCR_IntMul<SCR4RV64_MUL>;
+ defm : SCR_IntDiv<SCR4RV64_DIV, /* div latency = */ 11>;
+ defm : SCR_BasicMemory<SCR4RV64_LSU, /* load & store latency = */ 2>;
+ defm : SCR_FPMemory<SCR4RV64_LSU, /* load & store latency = */ 2>;
+ defm : SCR_AtomicMemory<SCR4RV64_LSU>;
+ defm : SCR_FPU<SCR4RV64_FPU>;
+ defm : SCR_FDU<SCR4RV64_FDU>;
+ defm : SCR_Other;
+
+ defm : SCR_Unsupported;
+ defm : SCR4_SCR5_NoReadAdvances;
+}
+
+//===----------------------------------------------------------------------===//
+// SCR5 scheduling model definition
+
+def SyntacoreSCR5RV32Model : SyntacoreSchedModel {
+ let LoadLatency = 3;
+}
+
+let SchedModel = SyntacoreSCR5RV32Model in {
+ let BufferSize = 0 in {
+ def SCR5RV32_ALU : ProcResource<1>;
+ def SCR5RV32_MUL : ProcResource<1>;
+ def SCR5RV32_DIV : ProcResource<1>;
+ def SCR5RV32_LSU : ProcResource<1>;
+ def SCR5RV32_CFU : ProcResource<1>;
+ def SCR5RV32_FPU : ProcResource<1>;
+ def SCR5RV32_FDU : ProcResource<1>; // FP div and sqrt resource
+ }
+
+ defm : SCR_Branching<SCR5RV32_CFU>;
+ defm : SCR_IntALU<SCR5RV32_ALU>;
+ defm : SCR_IntMul<SCR5RV32_MUL>;
+ defm : SCR_IntDiv<SCR5RV32_DIV, /* div latency = */ 8>;
+ defm : SCR_BasicMemory<SCR5RV32_LSU, /* load & store latency = */ 3>;
+ defm : SCR_FPMemory<SCR5RV32_LSU, /* load & store latency = */ 3>;
+ defm : SCR_AtomicMemory<SCR5RV32_LSU>;
+ defm : SCR_FPU<SCR5RV32_FPU>;
+ defm : SCR_FDU<SCR5RV32_FDU>;
+ defm : SCR_Other;
+
+ defm : SCR_Unsupported;
+ defm : SCR4_SCR5_NoReadAdvances;
+}
+
+def SyntacoreSCR5RV64Model : SyntacoreSchedModel {
+ let LoadLatency = 3;
+}
+
+let SchedModel = SyntacoreSCR5RV64Model in {
+ let BufferSize = 0 in {
+ def SCR5RV64_ALU : ProcResource<1>;
+ def SCR5RV64_MUL : ProcResource<1>;
+ def SCR5RV64_DIV : ProcResource<1>;
+ def SCR5RV64_LSU : ProcResource<1>;
+ def SCR5RV64_CFU : ProcResource<1>;
+ def SCR5RV64_FPU : ProcResource<1>;
+ def SCR5RV64_FDU : ProcResource<1>; // FP div and sqrt resource
+ }
+
+ defm : SCR_Branching<SCR5RV64_CFU>;
+ defm : SCR_IntALU<SCR5RV64_ALU>;
+ defm : SCR_IntMul<SCR5RV64_MUL>;
+ defm : SCR_IntDiv<SCR5RV64_DIV, /* div latency = */ 11>;
+ defm : SCR_BasicMemory<SCR5RV64_LSU, /* load & store latency = */ 3>;
+ defm : SCR_FPMemory<SCR5RV64_LSU, /* load & store latency = */ 3>;
+ defm : SCR_AtomicMemory<SCR5RV64_LSU>;
+ defm : SCR_FPU<SCR5RV64_FPU>;
+ defm : SCR_FDU<SCR5RV64_FDU>;
+ defm : SCR_Other;
+
+ defm : SCR_Unsupported;
+ defm : SCR4_SCR5_NoReadAdvances;
+}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s
deleted file mode 100644
index 83866106b47a17..00000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s
+++ /dev/null
@@ -1,91 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV64
-# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr3-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV32
-
-div a0, a0, a0
-mul t0, a0, t0
-add t1, a0, t0
-add t2, t2, t2
-div a1, a1, a1
-mul s0, a1, s0
-add s1, s0, s1
-add s2, s2, s2
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 8
-
-# RV32-NEXT: Total Cycles: 25
-# RV64-NEXT: Total Cycles: 31
-
-# CHECK-NEXT: Total uOps: 8
-
-# CHECK: Dispatch Width: 1
-
-# RV32-NEXT: uOps Per Cycle: 0.32
-# RV32-NEXT: IPC: 0.32
-# RV32-NEXT: Block RThroughput: 16.0
-
-# RV64-NEXT: uOps Per Cycle: 0.26
-# RV64-NEXT: IPC: 0.26
-# RV64-NEXT: Block RThroughput: 22.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-
-# RV32-NEXT: 1 8 8.00 div a0, a0, a0
-# RV64-NEXT: 1 11 11.00 div a0, a0, a0
-
-# CHECK-NEXT: 1 2 1.00 mul t0, a0, t0
-# CHECK-NEXT: 1 1 1.00 add t1, a0, t0
-# CHECK-NEXT: 1 1 1.00 add t2, t2, t2
-
-# RV32-NEXT: 1 8 8.00 div a1, a1, a1
-# RV64-NEXT: 1 11 11.00 div a1, a1, a1
-
-# CHECK-NEXT: 1 2 1.00 mul s0, a1, s0
-# CHECK-NEXT: 1 1 1.00 add s1, s1, s0
-# CHECK-NEXT: 1 1 1.00 add s2, s2, s2
-
-# CHECK: Resources:
-
-# RV32-NEXT: [0] - SCR3RV32_ALU
-# RV32-NEXT: [1] - SCR3RV32_CFU
-# RV32-NEXT: [2] - SCR3RV32_DIV
-# RV32-NEXT: [3] - SCR3RV32_LSU
-# RV32-NEXT: [4] - SCR3RV32_MUL
-
-# RV64-NEXT: [0] - SCR3RV64_ALU
-# RV64-NEXT: [1] - SCR3RV64_CFU
-# RV64-NEXT: [2] - SCR3RV64_DIV
-# RV64-NEXT: [3] - SCR3RV64_LSU
-# RV64-NEXT: [4] - SCR3RV64_MUL
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4]
-
-# RV32-NEXT: 4.00 - 16.00 - 2.00
-# RV64-NEXT: 4.00 - 22.00 - 2.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] Instructions:
-
-# RV32-NEXT: - - 8.00 - - div a0, a0, a0
-# RV64-NEXT: - - 11.00 - - div a0, a0, a0
-
-# CHECK-NEXT: - - - - 1.00 mul t0, a0, t0
-# CHECK-NEXT: 1.00 - - - - add t1, a0, t0
-# CHECK-NEXT: 1.00 - - - - add t2, t2, t2
-
-# RV32-NEXT: - - 8.00 - - div a1, a1, a1
-# RV64-NEXT: - - 11.00 - - div a1, a1, a1
-
-# CHECK-NEXT: - - - - 1.00 mul s0, a1, s0
-# CHECK-NEXT: 1.00 - - - - add s1, s1, s0
-# CHECK-NEXT: 1.00 - - - - add s2, s2, s2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s
deleted file mode 100644
index dc8ff80198ea5e..00000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s
+++ /dev/null
@@ -1,57 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV64
-# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr3-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV32
-
-lw a0, 0(s0)
-lw a1, 0(s0)
-lw a2, 0(s0)
-lw a3, 0(s0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 4
-# CHECK-NEXT: Total Cycles: 6
-# CHECK-NEXT: Total uOps: 4
-
-# CHECK: Dispatch Width: 1
-# CHECK-NEXT: uOps Per Cycle: 0.67
-# CHECK-NEXT: IPC: 0.67
-# CHECK-NEXT: Block RThroughput: 4.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 1.00 * lw a0, 0(s0)
-# CHECK-NEXT: 1 2 1.00 * lw a1, 0(s0)
-# CHECK-NEXT: 1 2 1.00 * lw a2, 0(s0)
-# CHECK-NEXT: 1 2 1.00 * lw a3, 0(s0)
-
-# CHECK: Resources:
-
-# RV32-NEXT: [0] - SCR3RV32_ALU
-# RV32-NEXT: [1] - SCR3RV32_CFU
-# RV32-NEXT: [2] - SCR3RV32_DIV
-# RV32-NEXT: [3] - SCR3RV32_LSU
-# RV32-NEXT: [4] - SCR3RV32_MUL
-
-# RV64-NEXT: [0] - SCR3RV64_ALU
-# RV64-NEXT: [1] - SCR3RV64_CFU
-# RV64-NEXT: [2] - SCR3RV64_DIV
-# RV64-NEXT: [3] - SCR3RV64_LSU
-# RV64-NEXT: [4] - SCR3RV64_MUL
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4]
-# CHECK-NEXT: - - - 4.00 -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] Instructions:
-# CHECK-NEXT: - - - 1.00 - lw a0, 0(s0)
-# CHECK-NEXT: - - - 1.00 - lw a1, 0(s0)
-# CHECK-NEXT: - - - 1.00 - lw a2, 0(s0)
-# CHECK-NEXT: - - - 1.00 - lw a3, 0(s0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-ALU.s b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-ALU.s
new file mode 100644
index 00000000000000..451402a917e3cc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-ALU.s
@@ -0,0 +1,164 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV64,SCR3_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr3-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV32,SCR3_32
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr4-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV64,SCR4_5_64,SCR4_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr4-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV32,SCR4_5_32,SCR4_32
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr5-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV64,SCR4_5_64,SCR5_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr5-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,RV32,SCR4_5_32,SCR5_32
+
+div a0, a0, a0
+mul t0, a0, t0
+add t1, a0, t0
+add t2, t2, t2
+div a1, a1, a1
+mul s0, a1, s0
+add s1, s0, s1
+add s2, s2, s2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 8
+
+# RV32-NEXT: Total Cycles: 25
+# RV64-NEXT: Total Cycles: 31
+
+# CHECK-NEXT: Total uOps: 8
+
+# CHECK: Dispatch Width: 1
+
+# RV32-NEXT: uOps Per Cycle: 0.32
+# RV32-NEXT: IPC: 0.32
+# RV32-NEXT: Block RThroughput: 16.0
+
+# RV64-NEXT: uOps Per Cycle: 0.26
+# RV64-NEXT: IPC: 0.26
+# RV64-NEXT: Block RThroughput: 22.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+
+# RV32-NEXT: 1 8 8.00 div a0, a0, a0
+# RV64-NEXT: 1 11 11.00 div a0, a0, a0
+
+# CHECK-NEXT: 1 2 1.00 mul t0, a0, t0
+# CHECK-NEXT: 1 1 1.00 add t1, a0, t0
+# CHECK-NEXT: 1 1 1.00 add t2, t2, t2
+
+# RV32-NEXT: 1 8 8.00 div a1, a1, a1
+# RV64-NEXT: 1 11 11.00 div a1, a1, a1
+
+# CHECK-NEXT: 1 2 1.00 mul s0, a1, s0
+# CHECK-NEXT: 1 1 1.00 add s1, s1, s0
+# CHECK-NEXT: 1 1 1.00 add s2, s2, s2
+
+# SCR3_32: Resources:
+# SCR3_32-NEXT: [0] - SCR3RV32_ALU
+# SCR3_32-NEXT: [1] - SCR3RV32_CFU
+# SCR3_32-NEXT: [2] - SCR3RV32_DIV
+# SCR3_32-NEXT: [3] - SCR3RV32_LSU
+# SCR3_32-NEXT: [4] - SCR3RV32_MUL
+
+# SCR3_64: Resources:
+# SCR3_64-NEXT: [0] - SCR3RV64_ALU
+# SCR3_64-NEXT: [1] - SCR3RV64_CFU
+# SCR3_64-NEXT: [2] - SCR3RV64_DIV
+# SCR3_64-NEXT: [3] - SCR3RV64_LSU
+# SCR3_64-NEXT: [4] - SCR3RV64_MUL
+
+# SCR4_32: Resources:
+# SCR4_32-NEXT: [0] - SCR4RV32_ALU
+# SCR4_32-NEXT: [1] - SCR4RV32_CFU
+# SCR4_32-NEXT: [2] - SCR4RV32_DIV
+# SCR4_32-NEXT: [3] - SCR4RV32_FDU
+# SCR4_32-NEXT: [4] - SCR4RV32_FPU
+# SCR4_32-NEXT: [5] - SCR4RV32_LSU
+# SCR4_32-NEXT: [6] - SCR4RV32_MUL
+
+# SCR4_64: Resources:
+# SCR4_64-NEXT: [0] - SCR4RV64_ALU
+# SCR4_64-NEXT: [1] - SCR4RV64_CFU
+# SCR4_64-NEXT: [2] - SCR4RV64_DIV
+# SCR4_64-NEXT: [3] - SCR4RV64_FDU
+# SCR4_64-NEXT: [4] - SCR4RV64_FPU
+# SCR4_64-NEXT: [5] - SCR4RV64_LSU
+# SCR4_64-NEXT: [6] - SCR4RV64_MUL
+
+# SCR5_32: Resources:
+# SCR5_32-NEXT: [0] - SCR5RV32_ALU
+# SCR5_32-NEXT: [1] - SCR5RV32_CFU
+# SCR5_32-NEXT: [2] - SCR5RV32_DIV
+# SCR5_32-NEXT: [3] - SCR5RV32_FDU
+# SCR5_32-NEXT: [4] - SCR5RV32_FPU
+# SCR5_32-NEXT: [5] - SCR5RV32_LSU
+# SCR5_32-NEXT: [6] - SCR5RV32_MUL
+
+# SCR5_64: Resources:
+# SCR5_64-NEXT: [0] - SCR5RV64_ALU
+# SCR5_64-NEXT: [1] - SCR5RV64_CFU
+# SCR5_64-NEXT: [2] - SCR5RV64_DIV
+# SCR5_64-NEXT: [3] - SCR5RV64_FDU
+# SCR5_64-NEXT: [4] - SCR5RV64_FPU
+# SCR5_64-NEXT: [5] - SCR5RV64_LSU
+# SCR5_64-NEXT: [6] - SCR5RV64_MUL
+
+# CHECK: Resource pressure per iteration:
+
+# SCR3_32-NEXT: [0] [1] [2] [3] [4]
+# SCR3_32-NEXT: 4.00 - 16.00 - 2.00
+
+# SCR3_64-NEXT: [0] [1] [2] [3] [4]
+# SCR3_64-NEXT: 4.00 - 22.00 - 2.00
+
+# SCR4_5_32-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR4_5_32-NEXT: 4.00 - 16.00 - - - 2.00
+
+# SCR4_5_64-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR4_5_64-NEXT: 4.00 - 22.00 - - - 2.00
+
+# CHECK: Resource pressure by instruction:
+
+# SCR3_32-NEXT: [0] [1] [2] [3] [4] Instructions:
+# SCR3_32-NEXT: - - 8.00 - - div a0, a0, a0
+# SCR3_32-NEXT: - - - - 1.00 mul t0, a0, t0
+# SCR3_32-NEXT: 1.00 - - - - add t1, a0, t0
+# SCR3_32-NEXT: 1.00 - - - - add t2, t2, t2
+# SCR3_32-NEXT: - - 8.00 - - div a1, a1, a1
+# SCR3_32-NEXT: - - - - 1.00 mul s0, a1, s0
+# SCR3_32-NEXT: 1.00 - - - - add s1, s1, s0
+# SCR3_32-NEXT: 1.00 - - - - add s2, s2, s2
+
+# SCR3_64-NEXT: [0] [1] [2] [3] [4] Instructions:
+# SCR3_64-NEXT: - - 11.00 - - div a0, a0, a0
+# SCR3_64-NEXT: - - - - 1.00 mul t0, a0, t0
+# SCR3_64-NEXT: 1.00 - - - - add t1, a0, t0
+# SCR3_64-NEXT: 1.00 - - - - add t2, t2, t2
+# SCR3_64-NEXT: - - 11.00 - - div a1, a1, a1
+# SCR3_64-NEXT: - - - - 1.00 mul s0, a1, s0
+# SCR3_64-NEXT: 1.00 - - - - add s1, s1, s0
+# SCR3_64-NEXT: 1.00 - - - - add s2, s2, s2
+
+# SCR4_5_32-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR4_5_32-NEXT: - - 8.00 - - - - div a0, a0, a0
+# SCR4_5_32-NEXT: - - - - - - 1.00 mul t0, a0, t0
+# SCR4_5_32-NEXT: 1.00 - - - - - - add t1, a0, t0
+# SCR4_5_32-NEXT: 1.00 - - - - - - add t2, t2, t2
+# SCR4_5_32-NEXT: - - 8.00 - - - - div a1, a1, a1
+# SCR4_5_32-NEXT: - - - - - - 1.00 mul s0, a1, s0
+# SCR4_5_32-NEXT: 1.00 - - - - - - add s1, s1, s0
+# SCR4_5_32-NEXT: 1.00 - - - - - - add s2, s2, s2
+
+# SCR4_5_64-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR4_5_64-NEXT: - - 11.00 - - - - div a0, a0, a0
+# SCR4_5_64-NEXT: - - - - - - 1.00 mul t0, a0, t0
+# SCR4_5_64-NEXT: 1.00 - - - - - - add t1, a0, t0
+# SCR4_5_64-NEXT: 1.00 - - - - - - add t2, t2, t2
+# SCR4_5_64-NEXT: - - 11.00 - - - - div a1, a1, a1
+# SCR4_5_64-NEXT: - - - - - - 1.00 mul s0, a1, s0
+# SCR4_5_64-NEXT: 1.00 - - - - - - add s1, s1, s0
+# SCR4_5_64-NEXT: 1.00 - - - - - - add s2, s2, s2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-LSU.s b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-LSU.s
new file mode 100644
index 00000000000000..38393a13ccc10e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-LSU.s
@@ -0,0 +1,176 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR3-4_64,SCR3_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr3-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR3-4_32,SCR3_32
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr4-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR3-4_64,SCR4_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr4-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR3-4_32,SCR4_32
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr5-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR5_64
+# RUN: llvm-mca -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr5-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR5_32
+
+lw a0, 0(s0)
+lw a1, 0(s0)
+lw a2, 0(s0)
+lw a3, 0(s0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 4
+
+# SCR3-4_32-NEXT: Total Cycles: 6
+# SCR3-4_64-NEXT: Total Cycles: 6
+# SCR5_32-NEXT: Total Cycles: 7
+# SCR5_64-NEXT: Total Cycles: 7
+
+# CHECK-NEXT: Total uOps: 4
+
+# CHECK: Dispatch Width: 1
+
+# SCR3-4_32-NEXT: uOps Per Cycle: 0.67
+# SCR3-4_32-NEXT: IPC: 0.67
+
+# SCR3-4_64-NEXT: uOps Per Cycle: 0.67
+# SCR3-4_64-NEXT: IPC: 0.67
+
+# SCR5_32-NEXT: uOps Per Cycle: 0.57
+# SCR5_32-NEXT: IPC: 0.57
+
+# SCR5_64-NEXT: uOps Per Cycle: 0.57
+# SCR5_64-NEXT: IPC: 0.57
+
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+
+# SCR3-4_32-NEXT: 1 2 1.00 * lw a0, 0(s0)
+# SCR3-4_32-NEXT: 1 2 1.00 * lw a1, 0(s0)
+# SCR3-4_32-NEXT: 1 2 1.00 * lw a2, 0(s0)
+# SCR3-4_32-NEXT: 1 2 1.00 * lw a3, 0(s0)
+
+# SCR3-4_64-NEXT: 1 2 1.00 * lw a0, 0(s0)
+# SCR3-4_64-NEXT: 1 2 1.00 * lw a1, 0(s0)
+# SCR3-4_64-NEXT: 1 2 1.00 * lw a2, 0(s0)
+# SCR3-4_64-NEXT: 1 2 1.00 * lw a3, 0(s0)
+
+# SCR5_32-NEXT: 1 3 1.00 * lw a0, 0(s0)
+# SCR5_32-NEXT: 1 3 1.00 * lw a1, 0(s0)
+# SCR5_32-NEXT: 1 3 1.00 * lw a2, 0(s0)
+# SCR5_32-NEXT: 1 3 1.00 * lw a3, 0(s0)
+
+# SCR5_64-NEXT: 1 3 1.00 * lw a0, 0(s0)
+# SCR5_64-NEXT: 1 3 1.00 * lw a1, 0(s0)
+# SCR5_64-NEXT: 1 3 1.00 * lw a2, 0(s0)
+# SCR5_64-NEXT: 1 3 1.00 * lw a3, 0(s0)
+
+# SCR3_32: Resources:
+# SCR3_32-NEXT: [0] - SCR3RV32_ALU
+# SCR3_32-NEXT: [1] - SCR3RV32_CFU
+# SCR3_32-NEXT: [2] - SCR3RV32_DIV
+# SCR3_32-NEXT: [3] - SCR3RV32_LSU
+# SCR3_32-NEXT: [4] - SCR3RV32_MUL
+
+# SCR3_64: Resources:
+# SCR3_64-NEXT: [0] - SCR3RV64_ALU
+# SCR3_64-NEXT: [1] - SCR3RV64_CFU
+# SCR3_64-NEXT: [2] - SCR3RV64_DIV
+# SCR3_64-NEXT: [3] - SCR3RV64_LSU
+# SCR3_64-NEXT: [4] - SCR3RV64_MUL
+
+# SCR4_32: Resources:
+# SCR4_32-NEXT: [0] - SCR4RV32_ALU
+# SCR4_32-NEXT: [1] - SCR4RV32_CFU
+# SCR4_32-NEXT: [2] - SCR4RV32_DIV
+# SCR4_32-NEXT: [3] - SCR4RV32_FDU
+# SCR4_32-NEXT: [4] - SCR4RV32_FPU
+# SCR4_32-NEXT: [5] - SCR4RV32_LSU
+# SCR4_32-NEXT: [6] - SCR4RV32_MUL
+
+# SCR4_64: Resources:
+# SCR4_64-NEXT: [0] - SCR4RV64_ALU
+# SCR4_64-NEXT: [1] - SCR4RV64_CFU
+# SCR4_64-NEXT: [2] - SCR4RV64_DIV
+# SCR4_64-NEXT: [3] - SCR4RV64_FDU
+# SCR4_64-NEXT: [4] - SCR4RV64_FPU
+# SCR4_64-NEXT: [5] - SCR4RV64_LSU
+# SCR4_64-NEXT: [6] - SCR4RV64_MUL
+
+# SCR5_32: Resources:
+# SCR5_32-NEXT: [0] - SCR5RV32_ALU
+# SCR5_32-NEXT: [1] - SCR5RV32_CFU
+# SCR5_32-NEXT: [2] - SCR5RV32_DIV
+# SCR5_32-NEXT: [3] - SCR5RV32_FDU
+# SCR5_32-NEXT: [4] - SCR5RV32_FPU
+# SCR5_32-NEXT: [5] - SCR5RV32_LSU
+# SCR5_32-NEXT: [6] - SCR5RV32_MUL
+
+# SCR5_64: Resources:
+# SCR5_64-NEXT: [0] - SCR5RV64_ALU
+# SCR5_64-NEXT: [1] - SCR5RV64_CFU
+# SCR5_64-NEXT: [2] - SCR5RV64_DIV
+# SCR5_64-NEXT: [3] - SCR5RV64_FDU
+# SCR5_64-NEXT: [4] - SCR5RV64_FPU
+# SCR5_64-NEXT: [5] - SCR5RV64_LSU
+# SCR5_64-NEXT: [6] - SCR5RV64_MUL
+
+# CHECK: Resource pressure per iteration:
+
+# SCR3_32-NEXT: [0] [1] [2] [3] [4]
+# SCR3_32-NEXT: - - - 4.00 -
+
+# SCR3_64-NEXT: [0] [1] [2] [3] [4]
+# SCR3_64-NEXT: - - - 4.00 -
+
+# SCR4_32-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR4_32-NEXT: - - - - - 4.00 -
+
+# SCR4_64-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR4_64-NEXT: - - - - - 4.00 -
+
+# SCR5_32-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR5_32-NEXT: - - - - - 4.00 -
+
+# SCR5_64-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# SCR5_64-NEXT: - - - - - 4.00 -
+
+# CHECK: Resource pressure by instruction:
+
+# SCR3_32-NEXT: [0] [1] [2] [3] [4] Instructions:
+# SCR3_32-NEXT: - - - 1.00 - lw a0, 0(s0)
+# SCR3_32-NEXT: - - - 1.00 - lw a1, 0(s0)
+# SCR3_32-NEXT: - - - 1.00 - lw a2, 0(s0)
+# SCR3_32-NEXT: - - - 1.00 - lw a3, 0(s0)
+
+# SCR3_64-NEXT: [0] [1] [2] [3] [4] Instructions:
+# SCR3_64-NEXT: - - - 1.00 - lw a0, 0(s0)
+# SCR3_64-NEXT: - - - 1.00 - lw a1, 0(s0)
+# SCR3_64-NEXT: - - - 1.00 - lw a2, 0(s0)
+# SCR3_64-NEXT: - - - 1.00 - lw a3, 0(s0)
+
+# SCR4_32-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR4_32-NEXT: - - - - - 1.00 - lw a0, 0(s0)
+# SCR4_32-NEXT: - - - - - 1.00 - lw a1, 0(s0)
+# SCR4_32-NEXT: - - - - - 1.00 - lw a2, 0(s0)
+# SCR4_32-NEXT: - - - - - 1.00 - lw a3, 0(s0)
+
+# SCR4_64-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR4_64-NEXT: - - - - - 1.00 - lw a0, 0(s0)
+# SCR4_64-NEXT: - - - - - 1.00 - lw a1, 0(s0)
+# SCR4_64-NEXT: - - - - - 1.00 - lw a2, 0(s0)
+# SCR4_64-NEXT: - - - - - 1.00 - lw a3, 0(s0)
+
+# SCR5_32-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR5_32-NEXT: - - - - - 1.00 - lw a0, 0(s0)
+# SCR5_32-NEXT: - - - - - 1.00 - lw a1, 0(s0)
+# SCR5_32-NEXT: - - - - - 1.00 - lw a2, 0(s0)
+# SCR5_32-NEXT: - - - - - 1.00 - lw a3, 0(s0)
+
+# SCR5_64-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# SCR5_64-NEXT: - - - - - 1.00 - lw a0, 0(s0)
+# SCR5_64-NEXT: - - - - - 1.00 - lw a1, 0(s0)
+# SCR5_64-NEXT: - - - - - 1.00 - lw a2, 0(s0)
+# SCR5_64-NEXT: - - - - - 1.00 - lw a3, 0(s0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s
new file mode 100644
index 00000000000000..90fef749a1c3dd
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s
@@ -0,0 +1,161 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca --timeline -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr4-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR4_64
+# RUN: llvm-mca --timeline -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr4-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR4_32
+# RUN: llvm-mca --timeline -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr5-rv64 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR5_64
+# RUN: llvm-mca --timeline -mtriple=riscv32-unknown-unknown -mcpu=syntacore-scr5-rv32 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK,SCR5_32
+
+fadd.s ft0, ft0, ft0
+fadd.d ft1, ft1, ft1
+fmul.s ft2, ft2, ft2
+fmul.d ft3, ft3, ft3
+fmadd.s ft4, ft4, ft4, ft4
+fmadd.d ft5, ft5, ft5, ft5
+fdiv.s ft6, ft6, ft6
+fdiv.d ft7, ft7, ft7
+fadd.s ft0, ft0, ft0
+fadd.d ft1, ft1, ft1
+fmul.s ft2, ft2, ft2
+fmul.d ft3, ft3, ft3
+fmadd.s ft4, ft4, ft4, ft4
+fmadd.d ft5, ft5, ft5, ft5
+fdiv.s ft6, ft6, ft6
+fdiv.d ft7, ft7, ft7
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 16
+# CHECK-NEXT: Total Cycles: 60
+# CHECK-NEXT: Total uOps: 16
+
+# CHECK: Dispatch Width: 1
+# CHECK-NEXT: uOps Per Cycle: 0.27
+# CHECK-NEXT: IPC: 0.27
+# CHECK-NEXT: Block RThroughput: 46.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 fadd.s ft0, ft0, ft0
+# CHECK-NEXT: 1 3 1.00 fadd.d ft1, ft1, ft1
+# CHECK-NEXT: 1 4 1.00 fmul.s ft2, ft2, ft2
+# CHECK-NEXT: 1 4 1.00 fmul.d ft3, ft3, ft3
+# CHECK-NEXT: 1 4 1.00 fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: 1 4 1.00 fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: 1 10 8.00 fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: 1 17 15.00 fdiv.d ft7, ft7, ft7
+# CHECK-NEXT: 1 3 1.00 fadd.s ft0, ft0, ft0
+# CHECK-NEXT: 1 3 1.00 fadd.d ft1, ft1, ft1
+# CHECK-NEXT: 1 4 1.00 fmul.s ft2, ft2, ft2
+# CHECK-NEXT: 1 4 1.00 fmul.d ft3, ft3, ft3
+# CHECK-NEXT: 1 4 1.00 fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: 1 4 1.00 fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: 1 10 8.00 fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: 1 17 15.00 fdiv.d ft7, ft7, ft7
+
+# CHECK: Resources:
+
+# SCR4_32-NEXT: [0] - SCR4RV32_ALU
+# SCR4_32-NEXT: [1] - SCR4RV32_CFU
+# SCR4_32-NEXT: [2] - SCR4RV32_DIV
+# SCR4_32-NEXT: [3] - SCR4RV32_FDU
+# SCR4_32-NEXT: [4] - SCR4RV32_FPU
+# SCR4_32-NEXT: [5] - SCR4RV32_LSU
+# SCR4_32-NEXT: [6] - SCR4RV32_MUL
+
+# SCR4_64-NEXT: [0] - SCR4RV64_ALU
+# SCR4_64-NEXT: [1] - SCR4RV64_CFU
+# SCR4_64-NEXT: [2] - SCR4RV64_DIV
+# SCR4_64-NEXT: [3] - SCR4RV64_FDU
+# SCR4_64-NEXT: [4] - SCR4RV64_FPU
+# SCR4_64-NEXT: [5] - SCR4RV64_LSU
+# SCR4_64-NEXT: [6] - SCR4RV64_MUL
+
+# SCR5_32-NEXT: [0] - SCR5RV32_ALU
+# SCR5_32-NEXT: [1] - SCR5RV32_CFU
+# SCR5_32-NEXT: [2] - SCR5RV32_DIV
+# SCR5_32-NEXT: [3] - SCR5RV32_FDU
+# SCR5_32-NEXT: [4] - SCR5RV32_FPU
+# SCR5_32-NEXT: [5] - SCR5RV32_LSU
+# SCR5_32-NEXT: [6] - SCR5RV32_MUL
+
+# SCR5_64-NEXT: [0] - SCR5RV64_ALU
+# SCR5_64-NEXT: [1] - SCR5RV64_CFU
+# SCR5_64-NEXT: [2] - SCR5RV64_DIV
+# SCR5_64-NEXT: [3] - SCR5RV64_FDU
+# SCR5_64-NEXT: [4] - SCR5RV64_FPU
+# SCR5_64-NEXT: [5] - SCR5RV64_LSU
+# SCR5_64-NEXT: [6] - SCR5RV64_MUL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# CHECK-NEXT: - - - 46.00 12.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - fadd.s ft0, ft0, ft0
+# CHECK-NEXT: - - - - 1.00 - - fadd.d ft1, ft1, ft1
+# CHECK-NEXT: - - - - 1.00 - - fmul.s ft2, ft2, ft2
+# CHECK-NEXT: - - - - 1.00 - - fmul.d ft3, ft3, ft3
+# CHECK-NEXT: - - - - 1.00 - - fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: - - - - 1.00 - - fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: - - - 8.00 - - - fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: - - - 15.00 - - - fdiv.d ft7, ft7, ft7
+# CHECK-NEXT: - - - - 1.00 - - fadd.s ft0, ft0, ft0
+# CHECK-NEXT: - - - - 1.00 - - fadd.d ft1, ft1, ft1
+# CHECK-NEXT: - - - - 1.00 - - fmul.s ft2, ft2, ft2
+# CHECK-NEXT: - - - - 1.00 - - fmul.d ft3, ft3, ft3
+# CHECK-NEXT: - - - - 1.00 - - fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: - - - - 1.00 - - fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: - - - 8.00 - - - fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: - - - 15.00 - - - fdiv.d ft7, ft7, ft7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789
+
+# CHECK: [0,0] DeeE . . . . . . . . . . . . fadd.s ft0, ft0, ft0
+# CHECK-NEXT: [0,1] .DeeE. . . . . . . . . . . . fadd.d ft1, ft1, ft1
+# CHECK-NEXT: [0,2] . DeeeE . . . . . . . . . . . fmul.s ft2, ft2, ft2
+# CHECK-NEXT: [0,3] . DeeeE . . . . . . . . . . . fmul.d ft3, ft3, ft3
+# CHECK-NEXT: [0,4] . DeeeE . . . . . . . . . . . fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: [0,5] . DeeeE. . . . . . . . . . . fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: [0,6] . .DeeeeeeeeeE . . . . . . . . . fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: [0,7] . . . DeeeeeeeeeeeeeeeeE . . . . . . fdiv.d ft7, ft7, ft7
+# CHECK-NEXT: [0,8] . . . . . . DeeE . . . . . . fadd.s ft0, ft0, ft0
+# CHECK-NEXT: [0,9] . . . . . . DeeE . . . . . . fadd.d ft1, ft1, ft1
+# CHECK-NEXT: [0,10] . . . . . . DeeeE. . . . . . fmul.s ft2, ft2, ft2
+# CHECK-NEXT: [0,11] . . . . . . .DeeeE . . . . . fmul.d ft3, ft3, ft3
+# CHECK-NEXT: [0,12] . . . . . . . DeeeE . . . . . fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: [0,13] . . . . . . . DeeeE . . . . . fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: [0,14] . . . . . . . DeeeeeeeeeE. . . . fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: [0,15] . . . . . . . . . DeeeeeeeeeeeeeeeeE fdiv.d ft7, ft7, ft7
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 fadd.s ft0, ft0, ft0
+# CHECK-NEXT: 1. 1 0.0 0.0 0.0 fadd.d ft1, ft1, ft1
+# CHECK-NEXT: 2. 1 0.0 0.0 0.0 fmul.s ft2, ft2, ft2
+# CHECK-NEXT: 3. 1 0.0 0.0 0.0 fmul.d ft3, ft3, ft3
+# CHECK-NEXT: 4. 1 0.0 0.0 0.0 fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: 5. 1 0.0 0.0 0.0 fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: 6. 1 0.0 0.0 0.0 fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: 7. 1 0.0 0.0 0.0 fdiv.d ft7, ft7, ft7
+# CHECK-NEXT: 8. 1 0.0 0.0 0.0 fadd.s ft0, ft0, ft0
+# CHECK-NEXT: 9. 1 0.0 0.0 0.0 fadd.d ft1, ft1, ft1
+# CHECK-NEXT: 10. 1 0.0 0.0 0.0 fmul.s ft2, ft2, ft2
+# CHECK-NEXT: 11. 1 0.0 0.0 0.0 fmul.d ft3, ft3, ft3
+# CHECK-NEXT: 12. 1 0.0 0.0 0.0 fmadd.s ft4, ft4, ft4, ft4
+# CHECK-NEXT: 13. 1 0.0 0.0 0.0 fmadd.d ft5, ft5, ft5, ft5
+# CHECK-NEXT: 14. 1 0.0 0.0 0.0 fdiv.s ft6, ft6, ft6
+# CHECK-NEXT: 15. 1 0.0 0.0 0.0 fdiv.d ft7, ft7, ft7
+# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
More information about the llvm-commits
mailing list