[llvm] [RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (PR #102802)

[Wang Yaduo via llvm-commits]

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@@ -1164,6 +1164,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     }
 
     unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
+    if (Subtarget->hasVendorXTHeadBb() && TrailingOnes > ShAmt) {
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MouseSplinter wrote:

Thanks! done

https://github.com/llvm/llvm-project/pull/102802