[llvm] 7ec9fa0 - [RISCV][GISel] Group the vector load/store legalizer actions together.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-13T13:49:19-07:00
New Revision: 7ec9fa03739db63b31d4d66e477afb964ddf690b

URL: https://github.com/llvm/llvm-project/commit/7ec9fa03739db63b31d4d66e477afb964ddf690b
DIFF: https://github.com/llvm/llvm-project/commit/7ec9fa03739db63b31d4d66e477afb964ddf690b.diff

LOG: [RISCV][GISel] Group the vector load/store legalizer actions together.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 4e583d96335d9f..ad36f822accefe 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -285,7 +285,22 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
                                      {s32, p0, s16, 16},
                                      {s32, p0, s32, 32},
                                      {p0, p0, sXLen, XLen}});
-  if (ST.hasVInstructions())
+  auto &ExtLoadActions =
+      getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
+          .legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 16}});
+  if (XLen == 64) {
+    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s8, 8},
+                                               {s64, p0, s16, 16},
+                                               {s64, p0, s32, 32},
+                                               {s64, p0, s64, 64}});
+    ExtLoadActions.legalForTypesWithMemDesc(
+        {{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
+  } else if (ST.hasStdExtD()) {
+    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
+  }
+
+  // Vector loads/stores.
+  if (ST.hasVInstructions()) {
     LoadStoreActions.legalForTypesWithMemDesc({{nxv2s8, p0, nxv2s8, 8},
                                                {nxv4s8, p0, nxv4s8, 8},
                                                {nxv8s8, p0, nxv8s8, 8},
@@ -302,38 +317,26 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
                                                {nxv8s32, p0, nxv8s32, 32},
                                                {nxv16s32, p0, nxv16s32, 32}});
 
-  auto &ExtLoadActions =
-      getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
-          .legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 16}});
-  if (XLen == 64) {
-    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s8, 8},
-                                               {s64, p0, s16, 16},
-                                               {s64, p0, s32, 32},
-                                               {s64, p0, s64, 64}});
-    ExtLoadActions.legalForTypesWithMemDesc(
-        {{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
-  } else if (ST.hasStdExtD()) {
-    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
-  }
-  if (ST.hasVInstructions() && ST.getELen() == 64)
-    LoadStoreActions.legalForTypesWithMemDesc({{nxv1s8, p0, nxv1s8, 8},
-                                               {nxv1s16, p0, nxv1s16, 16},
-                                               {nxv1s32, p0, nxv1s32, 32}});
+    if (ST.getELen() == 64)
+      LoadStoreActions.legalForTypesWithMemDesc({{nxv1s8, p0, nxv1s8, 8},
+                                                 {nxv1s16, p0, nxv1s16, 16},
+                                                 {nxv1s32, p0, nxv1s32, 32}});
 
-  if (ST.hasVInstructionsI64())
-    LoadStoreActions.legalForTypesWithMemDesc({{nxv1s64, p0, nxv1s64, 64},
+    if (ST.hasVInstructionsI64())
+      LoadStoreActions.legalForTypesWithMemDesc({{nxv1s64, p0, nxv1s64, 64},
+                                                 {nxv2s64, p0, nxv2s64, 64},
+                                                 {nxv4s64, p0, nxv4s64, 64},
+                                                 {nxv8s64, p0, nxv8s64, 64}});
 
-                                               {nxv2s64, p0, nxv2s64, 64},
-                                               {nxv4s64, p0, nxv4s64, 64},
-                                               {nxv8s64, p0, nxv8s64, 64}});
+    // we will take the custom lowering logic if we have scalable vector types
+    // with non-standard alignments
+    LoadStoreActions.customIf(
+          LegalityPredicates::any(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+                                  typeIsLegalPtrVec(0, PtrVecTys, ST)));
+  }
 
   LoadStoreActions.widenScalarToNextPow2(0, /* MinSize = */ 8)
       .lowerIfMemSizeNotByteSizePow2()
-      // we will take the custom lowering logic if we have scalable vector types
-      // with non-standard alignments
-      .customIf(LegalityPredicate(
-          LegalityPredicates::any(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
-                                  typeIsLegalPtrVec(0, PtrVecTys, ST))))
       .clampScalar(0, s32, sXLen)
       .lower();