[llvm] 51bad73 - [SelectionDAG] Replace EVTToAPFloatSemantics with MVT/EVT::getFltSemantics. (#103001)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 13 11:36:24 PDT 2024
Author: Craig Topper
Date: 2024-08-13T11:35:28-07:00
New Revision: 51bad732dc78d777b5dc25fd840f00b61110e4f2
URL: https://github.com/llvm/llvm-project/commit/51bad732dc78d777b5dc25fd840f00b61110e4f2
DIFF: https://github.com/llvm/llvm-project/commit/51bad732dc78d777b5dc25fd840f00b61110e4f2.diff
LOG: [SelectionDAG] Replace EVTToAPFloatSemantics with MVT/EVT::getFltSemantics. (#103001)
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 8757af4d6e96d..c762f09d55f16 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1819,12 +1819,6 @@ class SelectionDAG {
AllNodes.insert(Position, AllNodes.remove(N));
}
- /// Returns an APFloat semantics tag appropriate for the given type. If VT is
- /// a vector type, the element semantics are returned.
- static const fltSemantics &EVTToAPFloatSemantics(EVT VT) {
- return VT.getFltSemantics();
- }
-
/// Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void AddDbgValue(SDDbgValue *DB, bool isParameter);
@@ -2365,7 +2359,7 @@ class SelectionDAG {
/// Return the current function's default denormal handling kind for the given
/// floating point type.
DenormalMode getDenormalMode(EVT VT) const {
- return MF->getDenormalMode(EVTToAPFloatSemantics(VT));
+ return MF->getDenormalMode(VT.getFltSemantics());
}
bool shouldOptForSize() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1b9277a0fa509..0ce336c26c0ac 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17804,11 +17804,11 @@ static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) {
unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned;
unsigned OutputSize = (int)VT.getScalarSizeInBits();
unsigned ActualSize = std::min(InputSize, OutputSize);
- const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
+ const fltSemantics &Sem = N0.getValueType().getFltSemantics();
// We can only fold away the float conversion if the input range can be
// represented exactly in the float range.
- if (APFloat::semanticsPrecision(sem) >= ActualSize) {
+ if (APFloat::semanticsPrecision(Sem) >= ActualSize) {
if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) {
unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
: ISD::ZERO_EXTEND;
@@ -22599,7 +22599,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
KnownBits KnownElt = DAG.computeKnownBits(VecOp, EltMask);
if (KnownElt.isConstant()) {
APFloat CstFP =
- APFloat(DAG.EVTToAPFloatSemantics(ScalarVT), KnownElt.getConstant());
+ APFloat(ScalarVT.getFltSemantics(), KnownElt.getConstant());
if (TLI.isFPImmLegal(CstFP, ScalarVT))
return DAG.getConstantFP(CstFP, DL, ScalarVT);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f4b3d1a41c681..3eadfbf51ddaa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2435,7 +2435,7 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
EVT SetCCVT =
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ExpVT);
- const fltSemantics &FltSem = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &FltSem = VT.getFltSemantics();
const APFloat::ExponentType MaxExpVal = APFloat::semanticsMaxExponent(FltSem);
const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
@@ -2535,7 +2535,7 @@ SDValue SelectionDAGLegalize::expandFrexp(SDNode *Node) const {
if (AsIntVT == EVT()) // TODO: How to handle f80?
return SDValue();
- const fltSemantics &FltSem = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &FltSem = VT.getFltSemantics();
const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
const unsigned Precision = APFloat::semanticsPrecision(FltSem);
const unsigned BitSize = VT.getScalarSizeInBits();
@@ -2797,7 +2797,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
// The following optimization is valid only if every value in SrcVT (when
// treated as signed) is representable in DestVT. Check that the mantissa
// size of DestVT is >= than the number of bits in SrcVT -1.
- assert(APFloat::semanticsPrecision(DAG.EVTToAPFloatSemantics(DestVT)) >=
+ assert(APFloat::semanticsPrecision(DestVT.getFltSemantics()) >=
SrcVT.getSizeInBits() - 1 &&
"Cannot perform lossless SINT_TO_FP!");
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index edebb5ee87001..7c1cf129d5462 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1493,12 +1493,9 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
"Do not know how to expand this float constant!");
APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
SDLoc dl(N);
- Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
- APInt(64, C.getRawData()[1])),
- dl, NVT);
- Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
- APInt(64, C.getRawData()[0])),
- dl, NVT);
+ const fltSemantics &Sem = NVT.getFltSemantics();
+ Lo = DAG.getConstantFP(APFloat(Sem, APInt(64, C.getRawData()[1])), dl, NVT);
+ Hi = DAG.getConstantFP(APFloat(Sem, APInt(64, C.getRawData()[0])), dl, NVT);
}
void DAGTypeLegalizer::ExpandFloatRes_Unary(SDNode *N, RTLIB::Libcall LC,
@@ -1777,8 +1774,8 @@ void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
}
- Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
- APInt(NVT.getSizeInBits(), 0)), dl, NVT);
+ Lo = DAG.getConstantFP(
+ APFloat(NVT.getFltSemantics(), APInt(NVT.getSizeInBits(), 0)), dl, NVT);
if (IsStrict)
ReplaceValueWith(SDValue(N, 1), Chain);
@@ -1934,8 +1931,8 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
Chain = Hi.getValue(1);
// The low part is zero.
- Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
- APInt(NVT.getSizeInBits(), 0)), dl, NVT);
+ Lo = DAG.getConstantFP(
+ APFloat(NVT.getFltSemantics(), APInt(NVT.getSizeInBits(), 0)), dl, NVT);
// Modified the chain - switch anything that used the old chain to use the
// new one.
@@ -1964,8 +1961,8 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
// though.
if (SrcVT.bitsLE(MVT::i32)) {
// The integer can be represented exactly in an f64.
- Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
- APInt(NVT.getSizeInBits(), 0)), dl, NVT);
+ Lo = DAG.getConstantFP(
+ APFloat(NVT.getFltSemantics(), APInt(NVT.getSizeInBits(), 0)), dl, NVT);
if (Strict) {
Hi = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(NVT, MVT::Other),
{Chain, Src}, Flags);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f9701b3ccbffa..ab12c3b0e728a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -132,9 +132,8 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT,
// convert modifies in place, so make a copy.
APFloat Val2 = APFloat(Val);
bool losesInfo;
- (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
- APFloat::rmNearestTiesToEven,
- &losesInfo);
+ (void)Val2.convert(VT.getFltSemantics(), APFloat::rmNearestTiesToEven,
+ &losesInfo);
return !losesInfo;
}
@@ -1826,7 +1825,7 @@ SDValue SelectionDAG::getConstantFP(double Val, const SDLoc &DL, EVT VT,
EltVT == MVT::f16 || EltVT == MVT::bf16) {
bool Ignored;
APFloat APF = APFloat(Val);
- APF.convert(EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven,
+ APF.convert(EltVT.getFltSemantics(), APFloat::rmNearestTiesToEven,
&Ignored);
return getConstantFP(APF, DL, VT, isTarget);
}
@@ -6447,11 +6446,10 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
C->isOpaque());
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP: {
- APFloat apf(EVTToAPFloatSemantics(VT),
- APInt::getZero(VT.getSizeInBits()));
- (void)apf.convertFromAPInt(Val, Opcode == ISD::SINT_TO_FP,
+ APFloat FPV(VT.getFltSemantics(), APInt::getZero(VT.getSizeInBits()));
+ (void)FPV.convertFromAPInt(Val, Opcode == ISD::SINT_TO_FP,
APFloat::rmNearestTiesToEven);
- return getConstantFP(apf, DL, VT);
+ return getConstantFP(FPV, DL, VT);
}
case ISD::FP16_TO_FP:
case ISD::BF16_TO_FP: {
@@ -6462,8 +6460,8 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
- (void)FPV.convert(EVTToAPFloatSemantics(VT),
- APFloat::rmNearestTiesToEven, &Ignored);
+ (void)FPV.convert(VT.getFltSemantics(), APFloat::rmNearestTiesToEven,
+ &Ignored);
return getConstantFP(FPV, DL, VT);
}
case ISD::STEP_VECTOR:
@@ -6515,7 +6513,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
bool ignored;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
- (void)V.convert(EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
+ (void)V.convert(VT.getFltSemantics(), APFloat::rmNearestTiesToEven,
&ignored);
return getConstantFP(V, DL, VT);
}
@@ -6814,8 +6812,8 @@ SDValue SelectionDAG::foldConstantFPMath(unsigned Opcode, const SDLoc &DL,
bool Unused;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
- (void) C1.convert(EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
- &Unused);
+ (void)C1.convert(VT.getFltSemantics(), APFloat::rmNearestTiesToEven,
+ &Unused);
return getConstantFP(C1, DL, VT);
}
@@ -6836,7 +6834,7 @@ SDValue SelectionDAG::foldConstantFPMath(unsigned Opcode, const SDLoc &DL,
if (N1.isUndef() && N2.isUndef())
return getUNDEF(VT);
if (N1.isUndef() || N2.isUndef())
- return getConstantFP(APFloat::getNaN(EVTToAPFloatSemantics(VT)), DL, VT);
+ return getConstantFP(APFloat::getNaN(VT.getFltSemantics()), DL, VT);
}
return SDValue();
}
@@ -7661,8 +7659,7 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
!DAG.getTargetLoweringInfo().isLegalStoreImmediate(C->getSExtValue());
return DAG.getConstant(Val, dl, VT, false, IsOpaque);
}
- return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), dl,
- VT);
+ return DAG.getConstantFP(APFloat(VT.getFltSemantics(), Val), dl, VT);
}
assert(Value.getValueType() == MVT::i8 && "memset with non-byte fill value?");
@@ -11952,7 +11949,7 @@ bool llvm::isNeutralConstant(unsigned Opcode, SDNodeFlags Flags, SDValue V,
case ISD::FMAXNUM: {
// Neutral element for fminnum is NaN, Inf or FLT_MAX, depending on FMF.
EVT VT = V.getValueType();
- const fltSemantics &Semantics = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Semantics = VT.getFltSemantics();
APFloat NeutralAF = !Flags.hasNoNaNs()
? APFloat::getQNaN(Semantics)
: !Flags.hasNoInfs()
@@ -13228,7 +13225,7 @@ SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
case ISD::FMINNUM:
case ISD::FMAXNUM: {
// Neutral element for fminnum is NaN, Inf or FLT_MAX, depending on FMF.
- const fltSemantics &Semantics = EVTToAPFloatSemantics(VT);
+ const fltSemantics &Semantics = VT.getFltSemantics();
APFloat NeutralAF = !Flags.hasNoNaNs() ? APFloat::getQNaN(Semantics) :
!Flags.hasNoInfs() ? APFloat::getInf(Semantics) :
APFloat::getLargest(Semantics);
@@ -13240,7 +13237,7 @@ SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
case ISD::FMINIMUM:
case ISD::FMAXIMUM: {
// Neutral element for fminimum is Inf or FLT_MAX, depending on FMF.
- const fltSemantics &Semantics = EVTToAPFloatSemantics(VT);
+ const fltSemantics &Semantics = VT.getFltSemantics();
APFloat NeutralAF = !Flags.hasNoInfs() ? APFloat::getInf(Semantics)
: APFloat::getLargest(Semantics);
if (Opcode == ISD::FMAXIMUM)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 21d7a777653f1..c4f4261a708fd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2958,9 +2958,8 @@ bool TargetLowering::SimplifyDemandedBits(
return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
if (VT.isFloatingPoint())
return TLO.CombineTo(
- Op,
- TLO.DAG.getConstantFP(
- APFloat(TLO.DAG.EVTToAPFloatSemantics(VT), Known.One), dl, VT));
+ Op, TLO.DAG.getConstantFP(APFloat(VT.getFltSemantics(), Known.One),
+ dl, VT));
}
// A multi use 'all demanded elts' simplify failed to find any knownbits.
@@ -7236,7 +7235,7 @@ SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
// Testing it with denormal inputs to avoid wrong estimate.
//
// Test = fabs(X) < SmallestNormal
- const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT);
+ const fltSemantics &FltSem = VT.getFltSemantics();
APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem);
SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT);
SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op);
@@ -8273,7 +8272,7 @@ bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result,
// If the maximum float value is smaller then the signed integer range,
// the destination signmask can't be represented by the float, so we can
// just use FP_TO_SINT directly.
- const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT);
+ const fltSemantics &APFSem = SrcVT.getFltSemantics();
APFloat APF(APFSem, APInt::getZero(SrcVT.getScalarSizeInBits()));
APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits());
if (APFloat::opOverflow &
@@ -8518,8 +8517,8 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
// Propagate any NaN of both operands
if (!N->getFlags().hasNoNaNs() &&
(!DAG.isKnownNeverNaN(RHS) || !DAG.isKnownNeverNaN(LHS))) {
- ConstantFP *FPNaN = ConstantFP::get(
- *DAG.getContext(), APFloat::getNaN(DAG.EVTToAPFloatSemantics(VT)));
+ ConstantFP *FPNaN = ConstantFP::get(*DAG.getContext(),
+ APFloat::getNaN(VT.getFltSemantics()));
MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETUO),
DAG.getConstantFP(*FPNaN, DL, VT), MinMax, Flags);
}
@@ -11263,8 +11262,9 @@ SDValue TargetLowering::expandFP_TO_INT_SAT(SDNode *Node,
SrcVT = Src.getValueType();
}
- APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT));
- APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+ const fltSemantics &Sem = SrcVT.getFltSemantics();
+ APFloat MinFloat(Sem);
+ APFloat MaxFloat(Sem);
APFloat::opStatus MinStatus =
MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 314e7134dcd01..40d9fa4f2b494 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11471,8 +11471,7 @@ static SDValue getEstimate(const AArch64Subtarget *ST, unsigned Opcode,
// the result for float (23 mantissa bits) is 2 and for double (52
// mantissa bits) is 3.
constexpr unsigned AccurateBits = 8;
- unsigned DesiredBits =
- APFloat::semanticsPrecision(DAG.EVTToAPFloatSemantics(VT));
+ unsigned DesiredBits = APFloat::semanticsPrecision(VT.getFltSemantics());
ExtraSteps = DesiredBits <= AccurateBits
? 0
: Log2_64_Ceil(DesiredBits) - Log2_64_Ceil(AccurateBits);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index c82d1e2689978..8c8950957dd81 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2590,7 +2590,7 @@ SDValue AMDGPUTargetLowering::getIsLtSmallestNormal(SelectionDAG &DAG,
SDNodeFlags Flags) const {
SDLoc SL(Src);
EVT VT = Src.getValueType();
- const fltSemantics &Semantics = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Semantics = VT.getFltSemantics();
SDValue SmallestNormal =
DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT);
@@ -2607,7 +2607,7 @@ SDValue AMDGPUTargetLowering::getIsFinite(SelectionDAG &DAG, SDValue Src,
SDNodeFlags Flags) const {
SDLoc SL(Src);
EVT VT = Src.getValueType();
- const fltSemantics &Semantics = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Semantics = VT.getFltSemantics();
SDValue Inf = DAG.getConstantFP(APFloat::getInf(Semantics), SL, VT);
SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 7ce04d1dce8c1..86fc100f1c2da 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10872,8 +10872,8 @@ SDValue SITargetLowering::LowerFFREXP(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->hasFractBug()) {
SDValue Fabs = DAG.getNode(ISD::FABS, dl, VT, Val);
- SDValue Inf = DAG.getConstantFP(
- APFloat::getInf(SelectionDAG::EVTToAPFloatSemantics(VT)), dl, VT);
+ SDValue Inf =
+ DAG.getConstantFP(APFloat::getInf(VT.getFltSemantics()), dl, VT);
SDValue IsFinite = DAG.getSetCC(dl, MVT::i1, Fabs, Inf, ISD::SETOLT);
SDValue Zero = DAG.getConstant(0, dl, InstrExpVT);
@@ -12578,9 +12578,8 @@ SDValue SITargetLowering::performRcpCombine(SDNode *N,
SDValue N0 = N->getOperand(0);
if (N0.isUndef()) {
- return DCI.DAG.getConstantFP(
- APFloat::getQNaN(SelectionDAG::EVTToAPFloatSemantics(VT)), SDLoc(N),
- VT);
+ return DCI.DAG.getConstantFP(APFloat::getQNaN(VT.getFltSemantics()),
+ SDLoc(N), VT);
}
if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
@@ -12964,7 +12963,7 @@ SDValue SITargetLowering::performFCanonicalizeCombine(
// fcanonicalize undef -> qnan
if (N0.isUndef()) {
- APFloat QNaN = APFloat::getQNaN(SelectionDAG::EVTToAPFloatSemantics(VT));
+ APFloat QNaN = APFloat::getQNaN(VT.getFltSemantics());
return DAG.getConstantFP(QNaN, SDLoc(N), VT);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6fde09d89e483..a83138b3e0271 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2977,7 +2977,7 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
// Determine the largest integer that can be represented exactly. This and
// values larger than it don't have any fractional bits so don't need to
// be converted.
- const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(ContainerVT);
+ const fltSemantics &FltSem = ContainerVT.getFltSemantics();
unsigned Precision = APFloat::semanticsPrecision(FltSem);
APFloat MaxVal = APFloat(FltSem);
MaxVal.convertFromAPInt(APInt::getOneBitSet(Precision, Precision - 1),
@@ -3087,7 +3087,7 @@ lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
// Determine the largest integer that can be represented exactly. This and
// values larger than it don't have any fractional bits so don't need to
// be converted.
- const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(ContainerVT);
+ const fltSemantics &FltSem = ContainerVT.getFltSemantics();
unsigned Precision = APFloat::semanticsPrecision(FltSem);
APFloat MaxVal = APFloat(FltSem);
MaxVal.convertFromAPInt(APInt::getOneBitSet(Precision, Precision - 1),
@@ -3167,7 +3167,7 @@ lowerFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
// Create an integer the size of the mantissa with the MSB set. This and all
// values larger than it don't have any fractional bits so don't need to be
// converted.
- const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT);
+ const fltSemantics &FltSem = VT.getFltSemantics();
unsigned Precision = APFloat::semanticsPrecision(FltSem);
APFloat MaxVal = APFloat(FltSem);
MaxVal.convertFromAPInt(APInt::getOneBitSet(Precision, Precision - 1),
@@ -9598,8 +9598,7 @@ SDValue RISCVTargetLowering::lowerFPVECREDUCE(SDValue Op,
DAG.getConstant(0, DL, XLenVT), ISD::SETEQ);
return DAG.getSelect(
DL, ResVT, NoNaNs, Res,
- DAG.getConstantFP(APFloat::getNaN(DAG.EVTToAPFloatSemantics(ResVT)), DL,
- ResVT));
+ DAG.getConstantFP(APFloat::getNaN(ResVT.getFltSemantics()), DL, ResVT));
}
SDValue RISCVTargetLowering::lowerVPREDUCE(SDValue Op,
@@ -9648,8 +9647,7 @@ SDValue RISCVTargetLowering::lowerVPREDUCE(SDValue Op,
MVT ResVT = Res.getSimpleValueType();
return DAG.getSelect(
DL, ResVT, NoNaNs, Res,
- DAG.getConstantFP(APFloat::getNaN(DAG.EVTToAPFloatSemantics(ResVT)), DL,
- ResVT));
+ DAG.getConstantFP(APFloat::getNaN(ResVT.getFltSemantics()), DL, ResVT));
}
SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 04dfd0ea0d893..2759252693f9f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -10498,8 +10498,7 @@ static SDValue lowerShuffleAsBitMask(const SDLoc &DL, MVT VT, SDValue V1,
MVT LogicVT = VT;
if (EltVT == MVT::f32 || EltVT == MVT::f64) {
Zero = DAG.getConstantFP(0.0, DL, EltVT);
- APFloat AllOnesValue =
- APFloat::getAllOnesValue(SelectionDAG::EVTToAPFloatSemantics(EltVT));
+ APFloat AllOnesValue = APFloat::getAllOnesValue(EltVT.getFltSemantics());
AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
LogicVT =
MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
@@ -21338,8 +21337,9 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
MaxInt = APInt::getMaxValue(SatWidth).zext(DstWidth);
}
- APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT));
- APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+ const fltSemantics &Sem = SrcVT.getFltSemantics();
+ APFloat MinFloat(Sem);
+ APFloat MaxFloat(Sem);
APFloat::opStatus MinStatus = MinFloat.convertFromAPInt(
MinInt, IsSigned, APFloat::rmTowardZero);
@@ -21814,7 +21814,7 @@ static SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getSimpleValueType();
// N0 += copysign(nextafter(0.5, 0.0), N0)
- const fltSemantics &Sem = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Sem = VT.getFltSemantics();
bool Ignored;
APFloat Point5Pred = APFloat(0.5f);
Point5Pred.convert(Sem, APFloat::rmNearestTiesToEven, &Ignored);
@@ -21870,7 +21870,7 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
// For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
APInt MaskElt = IsFABS ? APInt::getSignedMaxValue(EltBits) :
APInt::getSignMask(EltBits);
- const fltSemantics &Sem = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Sem = VT.getFltSemantics();
SDValue Mask = DAG.getConstantFP(APFloat(Sem, MaskElt), dl, LogicVT);
SDValue Op0 = Op.getOperand(0);
@@ -21913,7 +21913,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
"Unexpected type in LowerFCOPYSIGN");
- const fltSemantics &Sem = SelectionDAG::EVTToAPFloatSemantics(VT);
+ const fltSemantics &Sem = VT.getFltSemantics();
// Perform all scalar logic operations as 16-byte vectors because there are no
// scalar FP logic instructions in SSE.
@@ -56091,7 +56091,7 @@ CastIntSETCCtoFP(MVT VT, ISD::CondCode CC, unsigned NumSignificantBitsLHS,
unsigned NumSignificantBitsRHS) {
MVT SVT = VT.getScalarType();
assert(SVT == MVT::f32 && "Only tested for float so far");
- const fltSemantics &Sem = SelectionDAG::EVTToAPFloatSemantics(SVT);
+ const fltSemantics &Sem = SVT.getFltSemantics();
assert((CC == ISD::SETEQ || CC == ISD::SETGT) &&
"Only PCMPEQ/PCMPGT currently supported");
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