[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)

[Mikael Holmén via llvm-commits]

================
@@ -1989,17 +1971,12 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
                                NVPTX::ST_f32_areg, NVPTX::ST_f64_areg);
     if (!Opcode)
       return false;
-    SDValue Ops[] = {Value,
-                     getI32Imm(CodeMemorySem, dl),
-                     getI32Imm(CodeAddrSpace, dl),
-                     getI32Imm(vecType, dl),
-                     getI32Imm(toType, dl),
-                     getI32Imm(toTypeWidth, dl),
-                     BasePtr,
-                     Chain};
-    NVPTXST = CurDAG->getMachineNode(*Opcode, dl, MVT::Other, Ops);
+    Ops.append({BasePtr, Chain});
   }
 
+  SDNode *NVPTXST = NVPTXST =
----------------
mikaelholmen wrote:

One assignment too much here?
gcc detects this and warns like
```
../lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp:1977:29: warning: operation on 'NVPTXST' may be undefined [-Wsequence-point]
 1977 |   SDNode *NVPTXST = NVPTXST =
      |                     ~~~~~~~~^
 1978 |       CurDAG->getMachineNode(*Opcode, DL, MVT::Other, Ops);
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```

https://github.com/llvm/llvm-project/pull/98551