[llvm] [AMDGPU] Use llvm::any_of, llvm::all_of, and llvm::none_of (NFC) (PR #103007)
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Mon Aug 12 23:18:13 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/103007.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (+6-6)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp (+10-16)
- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+4-5)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 3e1d1283dd485..25e36dc4b3691 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -1371,12 +1371,12 @@ bool AMDGPUCallLowering::lowerChainCall(MachineIRBuilder &MIRBuilder,
// The function that we're calling cannot be vararg (only the intrinsic is).
Info.IsVarArg = false;
- assert(std::all_of(SGPRArgs.Flags.begin(), SGPRArgs.Flags.end(),
- [](ISD::ArgFlagsTy F) { return F.isInReg(); }) &&
- "SGPR arguments should be marked inreg");
- assert(std::none_of(VGPRArgs.Flags.begin(), VGPRArgs.Flags.end(),
- [](ISD::ArgFlagsTy F) { return F.isInReg(); }) &&
- "VGPR arguments should not be marked inreg");
+ assert(
+ all_of(SGPRArgs.Flags, [](ISD::ArgFlagsTy F) { return F.isInReg(); }) &&
+ "SGPR arguments should be marked inreg");
+ assert(
+ none_of(VGPRArgs.Flags, [](ISD::ArgFlagsTy F) { return F.isInReg(); }) &&
+ "VGPR arguments should not be marked inreg");
SmallVector<ArgInfo, 8> OutArgs;
splitToValueTypes(SGPRArgs, OutArgs, DL, Info.CallConv);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 1ad2302a4f20c..4e913d1b32e1f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -955,10 +955,9 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
return false;
}
- auto Reaches = (std::any_of(
- Cache->begin(), Cache->end(), [&SU, &DAG](SUnit *TargetSU) {
- return DAG->IsReachable(TargetSU, const_cast<SUnit *>(SU));
- }));
+ auto Reaches = any_of(*Cache, [&SU, &DAG](SUnit *TargetSU) {
+ return DAG->IsReachable(TargetSU, const_cast<SUnit *>(SU));
+ });
return Reaches;
}
@@ -1477,10 +1476,9 @@ bool MFMAExpInterleaveOpt::analyzeDAG(const SIInstrInfo *TII) {
for (auto &MFMAPipeSU : MFMAPipeSUs) {
if (is_contained(MFMAChainSeeds, MFMAPipeSU))
continue;
- if (!std::any_of(MFMAPipeSU->Preds.begin(), MFMAPipeSU->Preds.end(),
- [&TII](SDep &Succ) {
- return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr());
- })) {
+ if (none_of(MFMAPipeSU->Preds, [&TII](SDep &Succ) {
+ return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr());
+ })) {
MFMAChainSeeds.push_back(MFMAPipeSU);
++MFMAChains;
}
@@ -1939,14 +1937,10 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
return true;
// Does the previous VALU have this DS_Write as a successor
- return (std::any_of(OtherGroup->Collection.begin(),
- OtherGroup->Collection.end(), [&SU](SUnit *Elt) {
- return std::any_of(Elt->Succs.begin(),
- Elt->Succs.end(),
- [&SU](SDep &Succ) {
- return Succ.getSUnit() == SU;
- });
- }));
+ return any_of(OtherGroup->Collection, [&SU](SUnit *Elt) {
+ return any_of(Elt->Succs,
+ [&SU](SDep &Succ) { return Succ.getSUnit() == SU; });
+ });
}
IsSuccOfPrevGroup(const SIInstrInfo *TII, unsigned SGID,
bool NeedsCache = false)
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 217279211531b..d6958d9055fad 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1647,11 +1647,10 @@ void GCNScheduleDAGMILive::updateRegionBoundaries(
}
static bool hasIGLPInstrs(ScheduleDAGInstrs *DAG) {
- return std::any_of(
- DAG->begin(), DAG->end(), [](MachineBasicBlock::iterator MI) {
- unsigned Opc = MI->getOpcode();
- return Opc == AMDGPU::SCHED_GROUP_BARRIER || Opc == AMDGPU::IGLP_OPT;
- });
+ return any_of(*DAG, [](MachineBasicBlock::iterator MI) {
+ unsigned Opc = MI->getOpcode();
+ return Opc == AMDGPU::SCHED_GROUP_BARRIER || Opc == AMDGPU::IGLP_OPT;
+ });
}
GCNPostScheduleDAGMILive::GCNPostScheduleDAGMILive(
``````````
</details>
https://github.com/llvm/llvm-project/pull/103007
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