[llvm] [LLVM][SelectionDAG] Remove scalable vector restriction from poison analysis. (PR #102504)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 12 23:02:49 PDT 2024
================
@@ -1501,18 +1501,23 @@ define <vscale x 8 x i32> @vwadd_vx_splat_zext_i1(<vscale x 8 x i1> %va, i16 %b)
; RV32: # %bb.0:
; RV32-NEXT: slli a0, a0, 16
; RV32-NEXT: srli a0, a0, 16
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v8, a0
-; RV32-NEXT: vadd.vi v8, v8, 1, v0.t
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-NEXT: ret
;
; RV64-LABEL: vwadd_vx_splat_zext_i1:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 48
; RV64-NEXT: srli a0, a0, 48
-; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV64-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; RV64-NEXT: vmv.v.x v12, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64-NEXT: vmv.v.x v8, a0
-; RV64-NEXT: vadd.vi v8, v8, 1, v0.t
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; RV64-NEXT: vwaddu.vx v8, v12, a0, v0.t
----------------
topperc wrote:
vzext.vf + vadd.vi seems like more work in the vector ALU. So I think vwaddu.vx w/immediate is better.
Hopefully we can find a way to fix this to match the RV32 codegen.
https://github.com/llvm/llvm-project/pull/102504
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