[llvm] [SLP][REVEC] Make computeMinimumValueSizes and collectValuesToDemote support vector instructions. (PR #103005)

Han-Kuan Chen via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 12 22:52:04 PDT 2024


https://github.com/HanKuanChen created https://github.com/llvm/llvm-project/pull/103005

None

>From 0dbe328a472d54babc360907383d6df3f6605449 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Thu, 25 Jul 2024 18:23:35 -0700
Subject: [PATCH 1/2] [SLP][REVEC] Pre-commit test.

---
 llvm/test/Transforms/SLPVectorizer/revec.ll | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/llvm/test/Transforms/SLPVectorizer/revec.ll b/llvm/test/Transforms/SLPVectorizer/revec.ll
index 4a72a5ff8395d..0c741fdebac9d 100644
--- a/llvm/test/Transforms/SLPVectorizer/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/revec.ll
@@ -222,3 +222,12 @@ entry:
   %cmp = icmp ugt <4 x i32> %vbsl, <i32 2, i32 3, i32 4, i32 5>
   ret <4 x i1> %cmp
 }
+
+define void @test7() {
+  %1 = getelementptr i8, ptr null, i64 16
+  %2 = trunc <8 x i64> zeroinitializer to <8 x i16>
+  store <8 x i16> %2, ptr %1, align 2
+  %3 = trunc <8 x i64> zeroinitializer to <8 x i16>
+  store <8 x i16> %3, ptr null, align 2
+  ret void
+}

>From 47c25f1221523d7b819baf627578a66067b0b46f Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Mon, 12 Aug 2024 22:30:14 -0700
Subject: [PATCH 2/2] [SLP][REVEC] Make computeMinimumValueSizes and
 collectValuesToDemote support vector instructions.

---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 9 ++++++---
 llvm/test/Transforms/SLPVectorizer/revec.ll     | 7 +++++++
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index cd89d5c63c40d..d4d53d1d7a6b8 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -15559,7 +15559,8 @@ bool BoUpSLP::collectValuesToDemote(
   if (all_of(E.Scalars, IsaPred<Constant>))
     return true;
 
-  unsigned OrigBitWidth = DL->getTypeSizeInBits(E.Scalars.front()->getType());
+  unsigned OrigBitWidth =
+      DL->getTypeSizeInBits(E.Scalars.front()->getType()->getScalarType());
   if (OrigBitWidth == BitWidth) {
     MaxDepthLevel = 1;
     return true;
@@ -15990,7 +15991,8 @@ void BoUpSLP::computeMinimumValueSizes() {
     }
 
     unsigned VF = E.getVectorFactor();
-    auto *TreeRootIT = dyn_cast<IntegerType>(E.Scalars.front()->getType());
+    auto *TreeRootIT =
+        dyn_cast<IntegerType>(E.Scalars.front()->getType()->getScalarType());
     if (!TreeRootIT || !Opcode)
       return 0u;
 
@@ -16140,7 +16142,8 @@ void BoUpSLP::computeMinimumValueSizes() {
 
     for (unsigned Idx : RootDemotes) {
       if (all_of(VectorizableTree[Idx]->Scalars, [&](Value *V) {
-            uint32_t OrigBitWidth = DL->getTypeSizeInBits(V->getType());
+            uint32_t OrigBitWidth =
+                DL->getTypeSizeInBits(V->getType()->getScalarType());
             if (OrigBitWidth > MaxBitWidth) {
               APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, MaxBitWidth);
               return MaskedValueIsZero(V, Mask, SimplifyQuery(*DL));
diff --git a/llvm/test/Transforms/SLPVectorizer/revec.ll b/llvm/test/Transforms/SLPVectorizer/revec.ll
index 0c741fdebac9d..9c8a98ba47b62 100644
--- a/llvm/test/Transforms/SLPVectorizer/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/revec.ll
@@ -224,6 +224,13 @@ entry:
 }
 
 define void @test7() {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i64> @llvm.vector.insert.v16i64.v8i64(<16 x i64> poison, <8 x i64> zeroinitializer, i64 0)
+; CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i64> @llvm.vector.insert.v16i64.v8i64(<16 x i64> [[TMP1]], <8 x i64> zeroinitializer, i64 8)
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc <16 x i64> [[TMP2]] to <16 x i16>
+; CHECK-NEXT:    store <16 x i16> [[TMP3]], ptr null, align 2
+; CHECK-NEXT:    ret void
+;
   %1 = getelementptr i8, ptr null, i64 16
   %2 = trunc <8 x i64> zeroinitializer to <8 x i16>
   store <8 x i16> %2, ptr %1, align 2



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