[llvm] [RFC][X86] Allow speculative BSR/BSF instructions on targets with CMOV (PR #102885)

[Craig Topper via llvm-commits]

topperc wrote:

It's been a while, but I think BSF/BSR may have a false dependency on the previous writer of the destination register on Intel CPUs. The behavior for the zero case is to leave the destination register unchanged so that requires the microarchitecture to copy the data to the renamed register.

https://github.com/llvm/llvm-project/pull/102885