[llvm] [Xtensa] Implement lowering Mul/Div/Shift operations. (PR #99981)

[Andrei Safronov via llvm-commits]

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@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define i32 @lshl(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: lshl:
+; CHECK:         ssl a3
+; CHECK-NEXT:    sll a2, a2
+; CHECK-NEXT:    ret
+  %c = shl i32 %x, %y
+  ret i32 %c
+}
+
+define i32 @lshl_imm_1(i32 %x) nounwind {
+; CHECK-LABEL: lshl_imm_1:
+; CHECK:         slli a2, a2, 1
+; CHECK-NEXT:    ret
+  %c = shl i32 %x, 1
+  ret i32 %c
+}
+
+define i32 @lshl_imm_10(i32 %x) nounwind {
+; CHECK-LABEL: lshl_imm_10:
+; CHECK:         slli a2, a2, 10
+; CHECK-NEXT:    ret
+  %c = shl i32 %x, 10
+  ret i32 %c
+}
+
+define i32 @lshl_imm_31(i32 %x) nounwind {
+; CHECK-LABEL: lshl_imm_31:
+; CHECK:         slli a2, a2, 31
+; CHECK-NEXT:    ret
+  %c = shl i32 %x, 31
+  ret i32 %c
+}
+
+define i32 @lshr(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: lshr:
+; CHECK:         ssr a3
+; CHECK-NEXT:    srl a2, a2
+; CHECK-NEXT:    ret
+  %c = lshr i32 %x, %y
+  ret i32 %c
+}
+
+define i32 @lshr_imm_1(i32 %x, i32 %y) nounwind {
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andreisfr wrote:

Fixed. Thank you. 

https://github.com/llvm/llvm-project/pull/99981