[llvm] [RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (PR #102909)

[Craig Topper via llvm-commits]

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+//==- RISCVSchedSyntacoreSCR345.td - Syntacore SCR3, SCR4, SCR5 Scheduling Definitions -*- tablegen -*-=//
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topperc wrote:

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https://github.com/llvm/llvm-project/pull/102909