[llvm] [LegalizeTypes] Reuse Op1 and Op2 variables to hold promoted values in PromoteIntRes_ADDSUBSHLSAT. NFC (PR #102840)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 12 10:03:15 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/102840
>From 17a0407a190fb1e5f30810d4d91370088234f538 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 11 Aug 2024 18:03:22 -0700
Subject: [PATCH 1/3] [LegalizeTypes] Reuse Op1 and Op2 variables to hold
promoted values in PromoteIntRes_ADDSUBSHLSAT. NFC
We don't need the original values after we promote them.
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 29 ++++++++-----------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 3635bc7a965804..27c8d7460db69c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1059,25 +1059,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
// FIXME: We need vp-aware PromotedInteger functions.
- SDValue Op1Promoted, Op2Promoted;
if (IsShift) {
- Op1Promoted = GetPromotedInteger(Op1);
- Op2Promoted = ZExtPromotedInteger(Op2);
+ Op1 = GetPromotedInteger(Op1);
+ Op2 = ZExtPromotedInteger(Op2);
} else if (Opcode == ISD::UADDSAT) {
- Op1Promoted = ZExtPromotedInteger(Op1);
- Op2Promoted = ZExtPromotedInteger(Op2);
+ Op1 = ZExtPromotedInteger(Op1);
+ Op2 = ZExtPromotedInteger(Op2);
} else {
- Op1Promoted = SExtPromotedInteger(Op1);
- Op2Promoted = SExtPromotedInteger(Op2);
+ Op1 = SExtPromotedInteger(Op1);
+ Op2 = SExtPromotedInteger(Op2);
}
- EVT PromotedType = Op1Promoted.getValueType();
+ EVT PromotedType = Op1.getValueType();
unsigned NewBits = PromotedType.getScalarSizeInBits();
if (Opcode == ISD::UADDSAT) {
APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
SDValue Add =
- matcher.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
+ matcher.getNode(ISD::ADD, dl, PromotedType, Op1, Op2);
return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
}
@@ -1102,14 +1101,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
unsigned SHLAmount = NewBits - OldBits;
SDValue ShiftAmount =
DAG.getShiftAmountConstant(SHLAmount, PromotedType, dl);
- Op1Promoted =
- DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
+ Op1 = DAG.getNode(ISD::SHL, dl, PromotedType, Op1, ShiftAmount);
if (!IsShift)
- Op2Promoted =
- matcher.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
+ Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
- SDValue Result =
- matcher.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
+ SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
}
@@ -1118,8 +1114,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
- SDValue Result =
- matcher.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
+ SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
return Result;
>From 705587dd2ed3f34a08e2ef513f29611425207326 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 11 Aug 2024 18:19:53 -0700
Subject: [PATCH 2/3] fixup! clang-format
---
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 27c8d7460db69c..0806de4efbf003 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1075,8 +1075,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
if (Opcode == ISD::UADDSAT) {
APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
- SDValue Add =
- matcher.getNode(ISD::ADD, dl, PromotedType, Op1, Op2);
+ SDValue Add = matcher.getNode(ISD::ADD, dl, PromotedType, Op1, Op2);
return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
}
>From 734ab91c2d553315beda4d4f3cd721bf8fcd27d2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 11 Aug 2024 19:12:05 -0700
Subject: [PATCH 3/3] [LegalizeTypes][RISCV] Use signed promotion for UADDSAT
if that's what the target prefers.
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 29 ++++++++++++-------
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++---
llvm/test/CodeGen/RISCV/uadd_sat_plus.ll | 2 +-
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0806de4efbf003..5b66748297b7ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1056,15 +1056,31 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
}
+ if (Opcode == ISD::UADDSAT) {
+ EVT OVT = Op1.getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
+ // We can promote if we use sign-extend. Do this if the target prefers.
+ if (TLI.isSExtCheaperThanZExt(OVT, NVT)) {
+ Op1 = SExtPromotedInteger(Op1);
+ Op2 = SExtPromotedInteger(Op2);
+ return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
+ }
+
+ Op1 = ZExtPromotedInteger(Op1);
+ Op2 = ZExtPromotedInteger(Op2);
+ unsigned NewBits = NVT.getScalarSizeInBits();
+ APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
+ SDValue SatMax = DAG.getConstant(MaxVal, dl, NVT);
+ SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
+ return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
+ }
+
bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
// FIXME: We need vp-aware PromotedInteger functions.
if (IsShift) {
Op1 = GetPromotedInteger(Op1);
Op2 = ZExtPromotedInteger(Op2);
- } else if (Opcode == ISD::UADDSAT) {
- Op1 = ZExtPromotedInteger(Op1);
- Op2 = ZExtPromotedInteger(Op2);
} else {
Op1 = SExtPromotedInteger(Op1);
Op2 = SExtPromotedInteger(Op2);
@@ -1072,13 +1088,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
EVT PromotedType = Op1.getValueType();
unsigned NewBits = PromotedType.getScalarSizeInBits();
- if (Opcode == ISD::UADDSAT) {
- APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
- SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
- SDValue Add = matcher.getNode(ISD::ADD, dl, PromotedType, Op1, Op2);
- return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
- }
-
// Shift cannot use a min/max expansion, we can't detect overflow if all of
// the bits have been shifted out.
if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 872c288f5ad8cd..4b21c192052dc9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -268,11 +268,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::LOAD, MVT::i32, Custom);
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
MVT::i32, Custom);
- setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT}, MVT::i32,
- Custom);
+ setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Custom);
if (!Subtarget.hasStdExtZbb())
- setOperationAction({ISD::SADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, MVT::i32,
- Custom);
+ setOperationAction(
+ {ISD::SADDSAT, ISD::SSUBSAT, ISD::UADDSAT, ISD::USUBSAT}, MVT::i32,
+ Custom);
setOperationAction(ISD::SADDO, MVT::i32, Custom);
}
if (!Subtarget.hasStdExtZmmul()) {
diff --git a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
index 219f0daf270bc1..23875a7ec56211 100644
--- a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
@@ -40,9 +40,9 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
;
; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sext.w a0, a0
; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: not a2, a1
-; RV64IZbb-NEXT: sext.w a0, a0
; RV64IZbb-NEXT: minu a0, a0, a2
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: ret
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