[llvm] [Xtensa] Implement lowering Mul/Div/Shift operations. (PR #99981)

[Andrei Safronov via llvm-commits]

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@@ -125,12 +125,75 @@ FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
 
 void XtensaDAGToDAGISel::Select(SDNode *Node) {
   SDLoc DL(Node);
+  EVT VT = Node->getValueType(0);
 
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
     Node->setNodeId(-1);
     return;
   }
 
+  switch (Node->getOpcode()) {
+  case ISD::SHL: {
+    SDValue N0 = Node->getOperand(0);
+    SDValue N1 = Node->getOperand(1);
+    if (!isa<ConstantSDNode>(N1)) {
+      SDNode *SSL = CurDAG->getMachineNode(Xtensa::SSL, DL, MVT::Glue, N1);
+      SDNode *SLL =
+          CurDAG->getMachineNode(Xtensa::SLL, DL, VT, N0, SDValue(SSL, 0));
+      ReplaceNode(Node, SLL);
+      return;
+    }
+    break;
+  }
+  case ISD::SRL: {
+    SDValue N0 = Node->getOperand(0);
+    SDValue N1 = Node->getOperand(1);
+    auto *C = dyn_cast<ConstantSDNode>(N1);
+    // If C is constant in range [0..15] then we can generate SRLI
+    // instruction using pattern matching, otherwise generate SRL
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andreisfr wrote:

The Xtensa SRLI (shift right by immediate) instruction encoding only support 4-bit shift immediate
"SRLI ar, at, 0..15 "
This immediate case is supported in instruction description
https://github.com/llvm/llvm-project/blob/8cf79c39c4b80efedad0f6eb84e04aca83d16154/llvm/lib/Target/Xtensa/XtensaInstrInfo.td#L160 
So, I created code for SRL case, which checks whether immediate fits to 0..15 range, in other case we should place shift amount in register

The SRAI (shift right arithmetic by immediate) instruction allows  encoding  of the shift immediate in 0..31 range
"SRAI ar, at, 0..31"
https://github.com/llvm/llvm-project/blob/8cf79c39c4b80efedad0f6eb84e04aca83d16154/llvm/lib/Target/Xtensa/XtensaInstrInfo.td#L151

The similar case is for SLLI instruction, it allows  encoding  of the shift immediate in 1..31 range
https://github.com/llvm/llvm-project/blob/8cf79c39c4b80efedad0f6eb84e04aca83d16154/llvm/lib/Target/Xtensa/XtensaInstrInfo.td#L168

https://github.com/llvm/llvm-project/pull/99981