[llvm] f9c9806 - [SPIR-V] Rework usage of virtual registers' types and classes (#101732)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 12 06:49:47 PDT 2024
Author: Vyacheslav Levytskyy
Date: 2024-08-12T15:49:43+02:00
New Revision: f9c98068c852c1bb1ec029c2c8df8ace9605f16f
URL: https://github.com/llvm/llvm-project/commit/f9c98068c852c1bb1ec029c2c8df8ace9605f16f
DIFF: https://github.com/llvm/llvm-project/commit/f9c98068c852c1bb1ec029c2c8df8ace9605f16f.diff
LOG: [SPIR-V] Rework usage of virtual registers' types and classes (#101732)
This PR contains changes in virtual register processing aimed to improve
correctness of emitted MIR between passes from the perspective of
MachineVerifier. This potentially helps to detect previously missed
flaws in code emission and harden the test suite. As a measure of
correctness and usefulness of this PR we may use a mode with expensive
checks set on, and MachineVerifier reports problems in the test suite.
In order to satisfy Machine Verifier requirements to MIR correctness not
only a rework of usage of virtual registers' types and classes is
required, but also corrections into pre-legalizer and instruction
selection logics. Namely, the following changes are introduced:
* scalar virtual registers have proper bit width,
* detect register class by SPIR-V type,
* add a superclass for id virtual register classes,
* fix Tablegen rules used for instruction selection,
* fixes of minor existed issues (missed flag for proper representation
of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual
registers as a synonym of any non-type virtual register).
Added:
Modified:
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
llvm/test/CodeGen/SPIRV/SampledImageRetType.ll
llvm/test/CodeGen/SPIRV/atomicrmw.ll
llvm/test/CodeGen/SPIRV/basic_int_types.ll
llvm/test/CodeGen/SPIRV/empty.ll
llvm/test/CodeGen/SPIRV/event-zero-const.ll
llvm/test/CodeGen/SPIRV/expect.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
llvm/test/CodeGen/SPIRV/instructions/atomic.ll
llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll
llvm/test/CodeGen/SPIRV/literals.ll
llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
llvm/test/CodeGen/SPIRV/opencl/image.ll
llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll
llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll
llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll
llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll
llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll
llvm/test/CodeGen/SPIRV/transcoding/non32.ll
llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll
llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll
llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll
llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll
llvm/test/CodeGen/SPIRV/types/or-i1.ll
llvm/test/CodeGen/SPIRV/unnamed-global.ll
llvm/test/CodeGen/SPIRV/var-uniform-const.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 8aea26d9963ceb..6dd0df2a104c0f 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -67,8 +67,7 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
// Check if we define an ID, and take a type as operand 1.
auto &DefOpInfo = MCDesc.operands()[0];
auto &FirstArgOpInfo = MCDesc.operands()[1];
- return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
- DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
+ return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
}
return false;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 1609576c038d01..c759fdcbd0a1ea 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -408,7 +408,7 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType,
Register ResultRegister =
MIRBuilder.getMRI()->createGenericVirtualRegister(Type);
- MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF());
return std::make_tuple(ResultRegister, BoolType);
}
@@ -442,7 +442,7 @@ static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister,
Register DestinationReg = Register(0)) {
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (!DestinationReg.isValid()) {
- DestinationReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ DestinationReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MRI->setType(DestinationReg, LLT::scalar(32));
GR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF());
}
@@ -460,7 +460,7 @@ static Register buildBuiltinVariableLoad(
SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType,
Register Reg = Register(0), bool isConst = true, bool hasLinkageTy = true) {
Register NewRegister =
- MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(NewRegister,
LLT::pointer(0, GR->getPointerSize()));
SPIRVType *PtrType = GR->getOrCreateSPIRVPointerType(
@@ -544,7 +544,7 @@ static Register buildScopeReg(Register CLScopeRegister,
Scope = getSPIRVScope(CLScope);
if (CLScope == static_cast<unsigned>(Scope)) {
- MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(CLScopeRegister, &SPIRV::iIDRegClass);
return CLScopeRegister;
}
}
@@ -564,7 +564,7 @@ static Register buildMemSemanticsReg(Register SemanticsRegister,
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
if (Order == Semantics) {
- MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(SemanticsRegister, &SPIRV::iIDRegClass);
return SemanticsRegister;
}
}
@@ -583,7 +583,7 @@ static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode,
for (unsigned i = 0; i < Sz; ++i) {
Register ArgReg = Call->Arguments[i];
if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
MIB.addUse(ArgReg);
}
for (uint32_t ImmArg : ImmArgs)
@@ -599,8 +599,8 @@ static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call,
assert(Call->Arguments.size() == 2 &&
"Need 2 arguments for atomic init translation");
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpStore)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
@@ -616,14 +616,14 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicLoad, Call, TypeReg);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
// TODO: if true insert call to __translate_ocl_memory_sccope before
// OpAtomicLoad and the function implementation. We can use Translator's
// output for transcoding/atomic_explicit_arguments.cl as an example.
Register ScopeRegister;
if (Call->Arguments.size() > 1) {
ScopeRegister = Call->Arguments[1];
- MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::iIDRegClass);
} else
ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -631,7 +631,7 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
if (Call->Arguments.size() > 2) {
// TODO: Insert call to __translate_ocl_memory_order before OpAtomicLoad.
MemSemanticsReg = Call->Arguments[2];
- MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else {
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
@@ -658,12 +658,12 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
Register ScopeRegister =
buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
.addUse(PtrRegister)
.addUse(ScopeRegister)
@@ -686,9 +686,9 @@ static bool buildAtomicCompareExchangeInst(
Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.)
Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected).
Register Desired = Call->Arguments[2]; // Value (C Desired).
- MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass);
- MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass);
- MRI->setRegClass(Desired, &SPIRV::IDRegClass);
+ MRI->setRegClass(ObjectPtr, &SPIRV::iIDRegClass);
+ MRI->setRegClass(ExpectedArg, &SPIRV::iIDRegClass);
+ MRI->setRegClass(Desired, &SPIRV::iIDRegClass);
SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired);
LLT DesiredLLT = MRI->getType(Desired);
@@ -729,8 +729,8 @@ static bool buildAtomicCompareExchangeInst(
MemSemEqualReg = Call->Arguments[3];
if (MemOrdNeq == MemSemEqual)
MemSemUnequalReg = Call->Arguments[4];
- MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[4], &SPIRV::iIDRegClass);
}
if (!MemSemEqualReg.isValid())
MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GR);
@@ -747,7 +747,7 @@ static bool buildAtomicCompareExchangeInst(
Scope = getSPIRVScope(ClScope);
if (ClScope == static_cast<unsigned>(Scope))
ScopeReg = Call->Arguments[5];
- MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[5], &SPIRV::iIDRegClass);
}
if (!ScopeReg.isValid())
ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
@@ -760,7 +760,7 @@ static bool buildAtomicCompareExchangeInst(
Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT)
: Call->ReturnRegister;
if (!MRI->getRegClassOrNull(Tmp))
- MRI->setRegClass(Tmp, &SPIRV::IDRegClass);
+ MRI->setRegClass(Tmp, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF());
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
@@ -799,12 +799,12 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register PtrRegister = Call->Arguments[0];
unsigned Semantics = SPIRV::MemorySemantics::None;
- MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
Register MemSemanticsReg =
Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
MemSemanticsReg = buildMemSemanticsReg(MemSemanticsReg, PtrRegister,
Semantics, MIRBuilder, GR);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
Register ValueReg = Call->Arguments[1];
Register ValueTypeReg = GR->getSPIRVTypeID(Call->ReturnType);
// support cl_ext_float_atomics
@@ -817,7 +817,7 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Opcode = SPIRV::OpAtomicFAddEXT;
Register NegValueReg =
MRI->createGenericVirtualRegister(MRI->getType(ValueReg));
- MRI->setRegClass(NegValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(NegValueReg, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(Call->ReturnType, NegValueReg,
MIRBuilder.getMF());
MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
@@ -849,16 +849,16 @@ static bool buildAtomicFloatingRMWInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register PtrReg = Call->Arguments[0];
- MRI->setRegClass(PtrReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(PtrReg, &SPIRV::iIDRegClass);
Register ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
Register MemSemanticsReg = Call->Arguments[2];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
Register ValueReg = Call->Arguments[3];
- MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
@@ -939,7 +939,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register MemSemanticsReg;
if (MemFlags == MemSemantics) {
MemSemanticsReg = Call->Arguments[0];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else
MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GR);
@@ -962,7 +962,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
if (CLScope == static_cast<unsigned>(Scope)) {
ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
}
}
@@ -1074,7 +1074,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
uint64_t GrpOp = MI->getOperand(1).getCImm()->getValue().getZExtValue();
Register ScopeReg = Call->Arguments[0];
if (!MRI->getRegClassOrNull(ScopeReg))
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
@@ -1083,7 +1083,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
for (unsigned i = 2; i < Call->Arguments.size(); ++i) {
Register ArgReg = Call->Arguments[i];
if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
MIB.addUse(ArgReg);
}
return true;
@@ -1131,10 +1131,10 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
MIB.addImm(GroupBuiltin->GroupOperation);
if (Call->Arguments.size() > 0) {
MIB.addUse(Arg0.isValid() ? Arg0 : Call->Arguments[0]);
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
for (unsigned i = 1; i < Call->Arguments.size(); i++) {
MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
}
}
@@ -1208,7 +1208,7 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
for (size_t i = 0; i < Call->Arguments.size(); ++i) {
MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
}
return true;
@@ -1232,11 +1232,11 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register GroupResultReg = Call->ReturnRegister;
- MRI->setRegClass(GroupResultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(GroupResultReg, &SPIRV::iIDRegClass);
// Scope
Register ScopeReg = Call->Arguments[0];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
// Group Operation
Register ConstGroupOpReg = Call->Arguments[1];
@@ -1253,7 +1253,7 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
// Value
Register ValueReg = Call->Arguments[2];
- MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(GroupUniform->Opcode)
.addDef(GroupResultReg)
@@ -1280,7 +1280,7 @@ static bool generateKernelClockInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register ResultReg = Call->ReturnRegister;
- MRI->setRegClass(ResultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ResultReg, &SPIRV::iIDRegClass);
// Deduce the `Scope` operand from the builtin function name.
SPIRV::Scope::Scope ScopeArg =
@@ -1350,7 +1350,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register DefaultReg = Call->ReturnRegister;
if (PointerSize != ResultWidth) {
DefaultReg = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(DefaultReg, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, DefaultReg,
MIRBuilder.getMF());
ToTruncate = DefaultReg;
@@ -1368,7 +1368,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register Extracted = Call->ReturnRegister;
if (!IsConstantIndex || PointerSize != ResultWidth) {
Extracted = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(Extracted, &SPIRV::IDRegClass);
+ MRI->setRegClass(Extracted, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, Extracted, MIRBuilder.getMF());
}
// Use Intrinsic::spv_extractelt so dynamic vs static extraction is
@@ -1387,7 +1387,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register CompareRegister =
MRI->createGenericVirtualRegister(LLT::scalar(1));
- MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(CompareRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF());
// Use G_ICMP to check if idxVReg < 3.
@@ -1404,7 +1404,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
if (PointerSize != ResultWidth) {
SelectionResult =
MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass);
+ MRI->setRegClass(SelectionResult, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, SelectionResult,
MIRBuilder.getMF());
}
@@ -1588,7 +1588,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
if (NumExpectedRetComponents != NumActualRetComponents) {
QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister(
LLT::fixed_vector(NumActualRetComponents, 32));
- MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::iIDRegClass);
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
QueryResultType = GR->getOrCreateSPIRVVectorType(
IntTy, NumActualRetComponents, MIRBuilder);
@@ -1597,7 +1597,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
bool IsDimBuf = ImgType->getOperand(2).getImm() == SPIRV::Dim::DIM_Buffer;
unsigned Opcode =
IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(Opcode)
.addDef(QueryResult)
.addUse(GR->getSPIRVTypeID(QueryResultType))
@@ -1653,7 +1653,7 @@ static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call,
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
Register Image = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::iIDRegClass);
SPIRV::Dim::Dim ImageDimensionality = static_cast<SPIRV::Dim::Dim>(
GR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm());
(void)ImageDimensionality;
@@ -1717,12 +1717,12 @@ static bool generateReadImageInst(const StringRef DemangledCall,
SPIRVGlobalRegistry *GR) {
Register Image = Call->Arguments[0];
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Image, &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Image, &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
bool HasOclSampler = DemangledCall.contains_insensitive("ocl_sampler");
bool HasMsaa = DemangledCall.contains_insensitive("msaa");
if (HasOclSampler || HasMsaa)
- MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
if (HasOclSampler) {
Register Sampler = Call->Arguments[1];
@@ -1738,7 +1738,7 @@ static bool generateReadImageInst(const StringRef DemangledCall,
SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image);
SPIRVType *SampledImageType =
GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
- Register SampledImage = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register SampledImage = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpSampledImage)
.addDef(SampledImage)
@@ -1757,7 +1757,7 @@ static bool generateReadImageInst(const StringRef DemangledCall,
}
LLT LLType = LLT::scalar(GR->getScalarOrVectorBitWidth(TempType));
Register TempRegister = MRI->createGenericVirtualRegister(LLType);
- MRI->setRegClass(TempRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(TempRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF());
MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
@@ -1795,9 +1795,9 @@ static bool generateReadImageInst(const StringRef DemangledCall,
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpImageWrite)
.addUse(Call->Arguments[0]) // Image.
.addUse(Call->Arguments[1]) // Coordinate.
@@ -1828,7 +1828,7 @@ static bool generateSampleImageInst(const StringRef DemangledCall,
Register SampledImage =
Call->ReturnRegister.isValid()
? Call->ReturnRegister
- : MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ : MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpSampledImage)
.addDef(SampledImage)
.addUse(GR->getSPIRVTypeID(SampledImageType))
@@ -1852,9 +1852,9 @@ static bool generateSampleImageInst(const StringRef DemangledCall,
"Unable to recognize SPIRV type name: " + ReturnType;
report_fatal_error(DiagMsg.c_str());
}
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
.addDef(Call->ReturnRegister)
@@ -1974,28 +1974,28 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
assert(PtrType->getOpcode() == SPIRV::OpTypePointer &&
PtrType->getOperand(2).isReg());
Register TypeReg = PtrType->getOperand(2).getReg();
SPIRVType *StructType = GR->getSPIRVTypeForVReg(TypeReg);
MachineFunction &MF = MIRBuilder.getMF();
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(StructType, TmpReg, MF);
// Skip the first arg, it's the destination pointer. OpBuildNDRange takes
// three other arguments, so pass zero constant on absence.
unsigned NumArgs = Call->Arguments.size();
assert(NumArgs >= 2);
Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
- MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass);
+ MRI->setRegClass(GlobalWorkSize, &SPIRV::iIDRegClass);
Register LocalWorkSize =
NumArgs == 2 ? Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
if (LocalWorkSize.isValid())
- MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass);
+ MRI->setRegClass(LocalWorkSize, &SPIRV::iIDRegClass);
Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1];
if (GlobalWorkOffset.isValid())
- MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass);
+ MRI->setRegClass(GlobalWorkOffset, &SPIRV::iIDRegClass);
if (NumArgs < 4) {
Register Const;
SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize);
@@ -2005,14 +2005,14 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
DefInstr->getOperand(3).isReg());
Register GWSPtr = DefInstr->getOperand(3).getReg();
if (!MRI->getRegClassOrNull(GWSPtr))
- MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
+ MRI->setRegClass(GWSPtr, &SPIRV::iIDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth);
Type *FieldTy = ArrayType::get(BaseTy, Size);
SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType(FieldTy, MIRBuilder);
- GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(SpvFieldTy, GlobalWorkSize, MF);
MIRBuilder.buildInstr(SPIRV::OpLoad)
.addDef(GlobalWorkSize)
@@ -2088,7 +2088,7 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
const SPIRVType *PointerSizeTy = GR->getOrCreateSPIRVPointerType(
Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
for (unsigned I = 0; I < LocalSizeNum; ++I) {
- Register Reg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register Reg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MRI->setType(Reg, LLType);
GR->assignSPIRVTypeToVReg(PointerSizeTy, Reg, MIRBuilder.getMF());
auto GEPInst = MIRBuilder.buildIntrinsic(
@@ -2154,7 +2154,7 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
switch (Opcode) {
case SPIRV::OpRetainEvent:
case SPIRV::OpReleaseEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode).addUse(Call->Arguments[0]);
case SPIRV::OpCreateUserEvent:
case SPIRV::OpGetDefaultQueue:
@@ -2162,21 +2162,21 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
case SPIRV::OpIsValidEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
.addUse(Call->Arguments[0]);
case SPIRV::OpSetUserEventStatus:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
case SPIRV::OpCaptureEventProfilingInfo:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1])
@@ -2389,21 +2389,21 @@ static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call,
// Add a pointer to the value to load/store.
MIB.addUse(Call->Arguments[0]);
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
// Add a value to store.
if (!IsLoad) {
MIB.addUse(Call->Arguments[1]);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
}
// Add optional memory attributes and an alignment.
unsigned NumArgs = Call->Arguments.size();
if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 1 : 2], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::iIDRegClass);
}
if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 2 : 3], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::iIDRegClass);
}
return true;
}
@@ -2496,7 +2496,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
if (OrigRetTy && !OrigRetTy->isVoidTy()) {
ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder);
if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister))
- MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::iIDRegClass);
} else if (OrigRetTy && OrigRetTy->isVoidTy()) {
ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(32));
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index de0b97fbea0c18..316abe866a163c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -372,7 +372,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
auto MRI = MIRBuilder.getMRI();
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
if (F.isDeclaration())
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
FunctionType *FTy = getOriginalFunctionType(F);
@@ -403,7 +403,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int i = 0;
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
- MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
+ MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
.addDef(VRegs[i][0])
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
@@ -558,7 +558,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
continue; // Don't handle zero sized types.
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(Reg, &SPIRV::IDRegClass);
+ MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
ToInsert.push_back({Reg});
VRegArgs.push_back(ToInsert.back());
}
@@ -596,7 +596,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// Make sure there's a valid return reg, even for functions returning void.
if (!ResVReg.isValid())
- ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
// Emit the call instruction and its args.
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index e70ddc4d394555..6702a0efc638ae 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -177,7 +177,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
else
@@ -214,7 +214,7 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
else
@@ -311,7 +311,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
- MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
SPIRV::AccessQualifier::ReadWrite, EmitIR);
DT.add(ConstInt, &MIRBuilder.getMF(), Res);
@@ -354,7 +354,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
Register Res = DT.find(ConstFP, &MF);
if (!Res.isValid()) {
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
- MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, MF);
DT.add(ConstFP, &MF, Res);
@@ -368,11 +368,9 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
return Res;
}
-Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
- MachineInstr &I,
- SPIRVType *SpvType,
- const SPIRVInstrInfo &TII,
- unsigned BitWidth) {
+Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
+ Constant *Val, MachineInstr &I, SPIRVType *SpvType,
+ const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
SPIRVType *Type = SpvType;
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
SpvType->getOpcode() == SPIRV::OpTypeArray) {
@@ -382,12 +380,12 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
if (Type->getOpcode() == SPIRV::OpTypeFloat) {
SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
assert(Type->getOpcode() == SPIRV::OpTypeInt);
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
@@ -404,14 +402,15 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
// TODO: can moved below once sorting of types/consts/defs is implemented.
Register SpvScalConst;
if (!IsNull)
- SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
+ SpvScalConst =
+ getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
MachineInstrBuilder MIB;
@@ -513,7 +512,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
if (EmitIR) {
@@ -565,7 +564,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
if (!Res.isValid()) {
LLT LLTy = LLT::pointer(LLVMPtrTy->getAddressSpace(), PointerSize);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
@@ -588,7 +587,7 @@ Register SPIRVGlobalRegistry::buildConstantSampler(
auto Sampler =
ResReg.isValid()
? ResReg
- : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
auto Res = MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
.addDef(Sampler)
.addUse(getSPIRVTypeID(SampTy))
@@ -1439,7 +1438,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
return Res;
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
DT.add(UV, CurMF, Res);
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 0e26b38225f7ac..821c1218fcb7f0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -439,8 +439,8 @@ class SPIRVGlobalRegistry {
SPIRVType *finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType);
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
- const SPIRVInstrInfo &TII,
- unsigned BitWidth);
+ const SPIRVInstrInfo &TII, unsigned BitWidth,
+ bool ZeroAsNull);
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII, Constant *CA,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 69d72a75a428a7..76419faa38e090 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -96,10 +96,10 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
: &SPIRV::fIDRegClass);
else if (VT.isInteger())
RC = VT.isVector() ? &SPIRV::vIDRegClass
- : (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
- : &SPIRV::IDRegClass);
+ : (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
+ : &SPIRV::iIDRegClass);
else
- RC = &SPIRV::IDRegClass;
+ RC = &SPIRV::iIDRegClass;
return std::make_pair(0u, RC);
}
@@ -125,7 +125,7 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
*STI.getRegBankInfo());
if (!Res)
report_fatal_error("insert validation bitcast: cannot constrain all uses");
- MRI->setRegClass(NewReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
I.getOperand(OpIdx).setReg(NewReg);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 63549b06e96700..c4b09dd6bfe430 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -17,8 +17,8 @@ include "SPIRVSymbolicOperands.td"
let isCodeGenOnly=1 in {
def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
- def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
- def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
+ def GET_ID: Pseudo<(outs iID:$dst_id), (ins ANYID:$src)>;
+ def GET_ID64: Pseudo<(outs iID64:$dst_id), (ins ANYID:$src)>;
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
@@ -40,18 +40,18 @@ class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
"$dst = "#name#" $src_ty $src $src2", pattern>;
class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
- "$dst = "#name#" $src_ty $src $src2", [(set ID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
+ "$dst = "#name#" $src_ty $src $src2", [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
- "$dst = "#name#" $src_ty $cond $src1 $src2", [(set ID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
+ "$dst = "#name#" $src_ty $cond $src1 $src2", [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
if genF then
def S: BinOpTyped<name, opCode, fID, node>;
else
- def S: BinOpTyped<name, opCode, ID, node>;
+ def S: BinOpTyped<name, opCode, iID, node>;
if genV then {
if genF then
def V: BinOpTyped<name, opCode, vfID, node>;
@@ -62,32 +62,32 @@ multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0
multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP = 1, bit genI = 1, bit genF = 0, bit genV = 0> {
if genF then {
- def SFSCond: TernOpTyped<name, opCode, ID, fID, node>;
+ def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
}
if genI then {
- def SISCond: TernOpTyped<name, opCode, ID, ID, node>;
- def SIVCond: TernOpTyped<name, opCode, vID, ID, node>;
+ def SISCond: TernOpTyped<name, opCode, iID, iID, node>;
+ def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
}
if genP then {
- def SPSCond32: TernOpTyped<name, opCode, ID, pID32, node>;
+ def SPSCond32: TernOpTyped<name, opCode, iID, pID32, node>;
def SPVCond32: TernOpTyped<name, opCode, vID, pID32, node>;
- def SPSCond64: TernOpTyped<name, opCode, ID, pID64, node>;
+ def SPSCond64: TernOpTyped<name, opCode, iID, pID64, node>;
def SPVCond64: TernOpTyped<name, opCode, vID, pID64, node>;
}
if genV then {
if genF then {
- def VFSCond: TernOpTyped<name, opCode, ID, vfID, node>;
+ def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
}
if genI then {
- def VISCond: TernOpTyped<name, opCode, ID, vID, node>;
+ def VISCond: TernOpTyped<name, opCode, iID, vID, node>;
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
}
if genP then {
- def VPSCond32: TernOpTyped<name, opCode, ID, vpID32, node>;
+ def VPSCond32: TernOpTyped<name, opCode, iID, vpID32, node>;
def VPVCond32: TernOpTyped<name, opCode, vID, vpID32, node>;
- def VPSCond64: TernOpTyped<name, opCode, ID, vpID64, node>;
+ def VPSCond64: TernOpTyped<name, opCode, iID, vpID64, node>;
def VPVCond64: TernOpTyped<name, opCode, vID, vpID64, node>;
}
}
@@ -97,8 +97,8 @@ class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
: Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
"$dst = "#name#" $type $src", pattern>;
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src),
- "$dst = "#name#" $src_ty $src", [(set ID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
+ "$dst = "#name#" $src_ty $src", [(set iID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;
@@ -240,16 +240,16 @@ def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.ge
def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
multiclass IntFPImm<bits<16> opCode, string name> {
- def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
- "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
- def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
- "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
+ def I: Op<opCode, (outs iID:$dst), (ins TYPE:$type, iID:$src, variable_ops),
+ "$dst = "#name#" $type", [(set iID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
+ def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
+ "$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}
-def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
-def OpConstantFalse: Op<42, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
+def OpConstantTrue: Op<41, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
+ [(set iID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
+def OpConstantFalse: Op<42, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
+ [(set iID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
defm OpConstant: IntFPImm<43, "OpConstant">;
@@ -258,8 +258,7 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
def OpConstantSampler: Op<45, (outs ID:$res),
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
"$res = OpConstantSampler $t $s $p $f">;
-def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
+def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;
def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
def OpSpecConstantFalse: Op<49, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantFalse $t">;
@@ -469,8 +468,10 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
// 3.42.12 Composite Instructions
+//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
+// "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
- "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
+ "$res = OpVectorExtractDynamic $type $vec $idx">;
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
@@ -521,8 +522,8 @@ def OpMatrixTimesMatrix: BinOp<"OpMatrixTimesMatrix", 146>;
def OpOuterProduct: BinOp<"OpOuterProduct", 147>;
def OpDot: BinOp<"OpDot", 148>;
-def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, ID, addc>;
-def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, ID, subc>;
+def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, iID, addc>;
+def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, iID, subc>;
def OpUMulExtended: BinOp<"OpUMulExtended", 151>;
def OpSMulExtended: BinOp<"OpSMulExtended", 152>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 5b04cc6661e49e..c55235a04a607f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -76,6 +76,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
SPIRVGlobalRegistry &GR;
MachineRegisterInfo *MRI;
SyncScopeIDs SSIDs;
+ MachineFunction *HasVRegsReset = nullptr;
/// We need to keep track of the number we give to anonymous global values to
/// generate the same name every time when this is needed.
@@ -101,6 +102,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
#undef GET_GLOBALISEL_TEMPORARIES_DECL
private:
+ void resetVRegsType(MachineFunction &MF);
+
// tblgen-erated 'select' implementation, used as the initial selector for
// the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
@@ -285,12 +288,48 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB,
InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
}
+// Ensure that register classes correspond to pattern matching rules.
+void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
+ if (HasVRegsReset == &MF)
+ return;
+ HasVRegsReset = &MF;
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ LLT Ty = MRI.getType(Reg);
+ if (Ty.isScalar())
+ MRI.setType(Reg, LLT::scalar(32));
+ else if (Ty.isVector() && !Ty.isPointer())
+ MRI.setType(Reg, LLT::scalar(32));
+ }
+ for (const auto &MBB : MF) {
+ for (const auto &MI : MBB) {
+ if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
+ continue;
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT DstType = MRI.getType(DstReg);
+ Register SrcReg = MI.getOperand(1).getReg();
+ LLT SrcType = MRI.getType(SrcReg);
+ if (DstType != SrcType)
+ MRI.setType(DstReg, MRI.getType(SrcReg));
+
+ const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
+ const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
+ if (DstRC != SrcRC && SrcRC)
+ MRI.setRegClass(DstReg, SrcRC);
+ }
+ }
+}
+
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI);
// Defined in SPIRVLegalizerInfo.cpp.
extern bool isTypeFoldingSupported(unsigned Opcode);
bool SPIRVInstructionSelector::select(MachineInstr &I) {
+ resetVRegsType(*I.getParent()->getParent());
+
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
@@ -309,6 +348,7 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (Res)
return Res;
}
+ MRI->setRegClass(DstReg, &SPIRV::iIDRegClass);
MRI->replaceRegWith(SrcReg, DstReg);
I.removeFromParent();
return true;
@@ -910,7 +950,7 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
Register ValueReg = I.getOperand(2).getReg();
if (NegateOpcode != 0) {
// Translation with negative value operand is requested
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
Result |= selectUnOpWithSrc(TmpReg, ResType, I, ValueReg, NegateOpcode);
ValueReg = TmpReg;
}
@@ -946,7 +986,7 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const {
if (!ResType) {
// There was no "assign type" actions, let's fix this now
ResType = ScalarType;
- MRI->setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType)));
GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
}
@@ -1007,7 +1047,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
Register Cmp = I.getOperand(3).getReg();
Register Val = I.getOperand(4).getReg();
SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val);
- Register ACmpRes = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register ACmpRes = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
const DebugLoc &DL = I.getDebugLoc();
bool Result =
BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange))
@@ -1020,7 +1060,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
.addUse(Val)
.addUse(Cmp)
.constrainAllUses(TII, TRI, RBI);
- Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII);
Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual))
.addDef(CmpSuccReg)
@@ -1028,7 +1068,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
.addUse(ACmpRes)
.addUse(Cmp)
.constrainAllUses(TII, TRI, RBI);
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
.addDef(TmpReg)
.addUse(GR.getSPIRVTypeID(ResType))
@@ -1117,7 +1157,7 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
// Casting between 2 eligible pointers using Generic as an intermediary.
if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
- Register Tmp = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register Tmp = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType(
GR.getPointeeType(SrcPtrTy), I, TII, SPIRV::StorageClass::Generic);
MachineBasicBlock &BB = *I.getParent();
@@ -1272,7 +1312,7 @@ bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
if (IsVectorTy) {
NotEqualReg = IsBoolTy ? InputRegister
- : MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ : MRI->createVirtualRegister(&SPIRV::iIDRegClass);
const unsigned NumElts = InputType->getOperand(2).getImm();
SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII);
}
@@ -1708,7 +1748,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
const unsigned NumElts = ResType->getOperand(2).getImm();
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
}
- SrcReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ SrcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
selectSelect(SrcReg, TmpType, I, false);
}
return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode);
@@ -1739,7 +1779,7 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg,
const SPIRVType *IntTy,
const SPIRVType *BoolTy) const {
// To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero.
- Register BitIntReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register BitIntReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector;
unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS;
Register Zero = buildZerosVal(IntTy, I);
@@ -1950,7 +1990,7 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
continue;
}
// Create a new register for the wrapper
- WrapReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ WrapReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR.add(OpDefine, MF, WrapReg);
CompositeArgs.push_back(WrapReg);
// Decorate the wrapper register and generate a new instruction
@@ -2262,7 +2302,7 @@ bool SPIRVInstructionSelector::selectGlobalValue(
// module analysis stage.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
MachineInstrBuilder MB =
BuildMI(BB, I, I.getDebugLoc(),
TII.get(SPIRV::OpConstantFunctionPointerINTEL))
@@ -2329,7 +2369,7 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
MachineBasicBlock &BB = *I.getParent();
// Build log2(x).
- Register VarReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register VarReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
bool Result =
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
.addDef(VarReg)
@@ -2380,7 +2420,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for GlobalInvocationID builtin variable.
Register NewRegister =
- MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 32));
GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
@@ -2393,7 +2433,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for loading value.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 32));
GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index c3842f0266706d..44685be3d68ad4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -102,7 +102,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!ResType) {
// There was no "assign type" actions, let's fix this now
ResType = ScalarType;
- MRI.setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI.setType(ResVReg,
LLT::scalar(GR->getScalarOrVectorBitWidth(ResType)));
GR->assignSPIRVTypeToVReg(ResType, ResVReg, *GR->CurMF);
@@ -124,7 +124,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!ResVType)
continue;
// Set type & class
- MRI.setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI.setType(ResVReg,
LLT::scalar(GR->getScalarOrVectorBitWidth(ResVType)));
GR->assignSPIRVTypeToVReg(ResVType, ResVReg, *GR->CurMF);
@@ -139,7 +139,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
// Restore usual instructions pattern for the newly inserted
// instruction
MRI.setRegClass(ResVReg, MRI.getType(ResVReg).isVector()
- ? &SPIRV::IDRegClass
+ ? &SPIRV::iIDRegClass
: &SPIRV::ANYIDRegClass);
MRI.setType(ResVReg, LLT::scalar(32));
insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI);
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 099557a6081854..6838f4bf9410f0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -225,17 +225,17 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineRegisterInfo &MRI,
MachineIRBuilder &MIB) {
- SPIRVType *SpirvTy = nullptr;
+ SPIRVType *SpvType = nullptr;
assert(MI && "Machine instr is expected");
if (MI->getOperand(0).isReg()) {
Register Reg = MI->getOperand(0).getReg();
- SpirvTy = GR->getSPIRVTypeForVReg(Reg);
- if (!SpirvTy) {
+ SpvType = GR->getSPIRVTypeForVReg(Reg);
+ if (!SpvType) {
switch (MI->getOpcode()) {
case TargetOpcode::G_CONSTANT: {
MIB.setInsertPt(*MI->getParent(), MI);
Type *Ty = MI->getOperand(1).getCImm()->getType();
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_GLOBAL_VALUE: {
@@ -244,7 +244,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
Type *ElementTy = toTypedPointer(GR->getDeducedGlobalValueType(Global));
auto *Ty = TypedPointerType::get(ElementTy,
Global->getType()->getAddressSpace());
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_ANYEXT:
@@ -258,17 +258,17 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
unsigned ExpectedBW =
std::max(MRI.getType(Reg).getScalarSizeInBits(), CurrentBW);
unsigned NumElements = GR->getScalarOrVectorComponentCount(Def);
- SpirvTy = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
+ SpvType = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
if (NumElements > 1)
- SpirvTy =
- GR->getOrCreateSPIRVVectorType(SpirvTy, NumElements, MIB);
+ SpvType =
+ GR->getOrCreateSPIRVVectorType(SpvType, NumElements, MIB);
}
}
}
break;
}
case TargetOpcode::G_PTRTOINT:
- SpirvTy = GR->getOrCreateSPIRVIntegerType(
+ SpvType = GR->getOrCreateSPIRVIntegerType(
MRI.getType(Reg).getScalarSizeInBits(), MIB);
break;
case TargetOpcode::G_TRUNC:
@@ -278,19 +278,19 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineOperand &Op = MI->getOperand(1);
MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
if (Def)
- SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
+ SpvType = propagateSPIRVType(Def, GR, MRI, MIB);
break;
}
default:
break;
}
- if (SpirvTy)
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ if (SpvType)
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ MRI.setRegClass(Reg, &SPIRV::iIDRegClass);
}
}
- return SpirvTy;
+ return SpvType;
}
// To support current approach and limitations wrt. bit width here we widen a
@@ -308,93 +308,104 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
MRI.setType(Reg, LLT::scalar(NewSz));
}
+inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
+ bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
+ return IsFloat ? true
+ : SpvType->getOpcode() == SPIRV::OpTypeVector &&
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
+ ->getOpcode() == SPIRV::OpTypeFloat;
+}
+
+static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
+ const SPIRVGlobalRegistry &GR) {
+ unsigned Opcode = SpvType->getOpcode();
+ switch (Opcode) {
+ case SPIRV::OpTypeFloat:
+ return &SPIRV::fIDRegClass;
+ case SPIRV::OpTypePointer:
+ return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
+ : &SPIRV::pID32RegClass;
+ case SPIRV::OpTypeVector: {
+ SPIRVType *ElemType =
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+ unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+ if (ElemOpcode == SPIRV::OpTypeFloat)
+ return &SPIRV::vfIDRegClass;
+ if (ElemOpcode == SPIRV::OpTypePointer)
+ return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
+ : &SPIRV::vpID32RegClass;
+ return &SPIRV::vIDRegClass;
+ }
+ }
+ return &SPIRV::iIDRegClass;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
if (!SpvType)
SpvType = GR.getSPIRVTypeForVReg(SrcReg);
assert(SpvType && "VReg is expected to have SPIRV type");
+ LLT NewT;
LLT SrcLLT = MRI.getType(SrcReg);
- LLT NewT = LLT::scalar(32);
- bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
- bool IsVectorFloat =
- SpvType->getOpcode() == SPIRV::OpTypeVector &&
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
- SPIRV::OpTypeFloat;
- IsFloat |= IsVectorFloat;
+ bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
- auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
if (SrcLLT.isPointer()) {
unsigned PtrSz = GR.getPointerSize();
NewT = LLT::pointer(0, PtrSz);
bool IsVec = SrcLLT.isVector();
if (IsVec)
NewT = LLT::fixed_vector(2, NewT);
- if (PtrSz == 64) {
- if (IsVec) {
- GetIdOp = SPIRV::GET_vpID64;
- DstClass = &SPIRV::vpID64RegClass;
- } else {
- GetIdOp = SPIRV::GET_pID64;
- DstClass = &SPIRV::pID64RegClass;
- }
- } else {
- if (IsVec) {
- GetIdOp = SPIRV::GET_vpID32;
- DstClass = &SPIRV::vpID32RegClass;
- } else {
- GetIdOp = SPIRV::GET_pID32;
- DstClass = &SPIRV::pID32RegClass;
- }
- }
+ if (PtrSz == 64)
+ GetIdOp = IsVec ? SPIRV::GET_vpID64 : SPIRV::GET_pID64;
+ else
+ GetIdOp = IsVec ? SPIRV::GET_vpID32 : SPIRV::GET_pID32;
} else if (SrcLLT.isVector()) {
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
NewT = LLT::fixed_vector(2, NewT);
- if (IsFloat) {
- GetIdOp = SPIRV::GET_vfID;
- DstClass = &SPIRV::vfIDRegClass;
- } else {
- GetIdOp = SPIRV::GET_vID;
- DstClass = &SPIRV::vIDRegClass;
- }
+ GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
+ } else {
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
- MRI.setRegClass(IdReg, DstClass);
+ MRI.setRegClass(IdReg, getRegClass(SpvType, GR));
return {IdReg, GetIdOp};
}
// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
-// a dst of the definition, assign SPIRVType to both registers. If SpirvTy is
+// a dst of the definition, assign SPIRVType to both registers. If SpvType is
// provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
// It's used also in SPIRVBuiltins.cpp.
// TODO: maybe move to SPIRVUtils.
namespace llvm {
-Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
+Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
MachineInstr *Def = MRI.getVRegDef(Reg);
- assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected.");
+ assert((Ty || SpvType) && "Either LLVM or SPIRV type is expected.");
MIB.setInsertPt(*Def->getParent(),
(Def->getNextNode() ? Def->getNextNode()->getIterator()
: Def->getParent()->end()));
- SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = SpvType ? SpvType : GR->getOrCreateSPIRVType(Ty, MIB);
Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg));
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ auto RegClass = getRegClass(SpvType, *GR);
+ MRI.setRegClass(NewReg, RegClass);
+ MRI.setRegClass(Reg, RegClass);
}
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
// when processing the actual MI (i.e. not pseudo one).
- GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, NewReg, MIB.getMF());
// Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
// the flags after instruction selection.
const uint32_t Flags = Def->getFlags();
MIB.buildInstr(SPIRV::ASSIGN_TYPE)
.addDef(Reg)
.addUse(NewReg)
- .addUse(GR->getSPIRVTypeID(SpirvTy))
+ .addUse(GR->getSPIRVTypeID(SpvType))
.setMIFlags(Flags);
Def->getOperand(0).setReg(NewReg);
return NewReg;
@@ -593,10 +604,6 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (!isTypeFoldingSupported(Opcode))
continue;
Register DstReg = MI.getOperand(0).getReg();
- bool IsDstPtr = MRI.getType(DstReg).isPointer();
- bool isDstVec = MRI.getType(DstReg).isVector();
- if (IsDstPtr || isDstVec)
- MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
// Don't need to reset type of register holding constant and used in
// G_ADDRSPACE_CAST, since it breaks legalizer.
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
@@ -604,8 +611,8 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
- : LLT::scalar(32));
+ if (MRI.getType(DstReg).isPointer())
+ MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
}
}
}
@@ -624,7 +631,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!AsmTargetReg.isValid()) {
// define vendor specific assembly target or dialect
AsmTargetReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(AsmTargetReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(AsmTargetReg, &SPIRV::iIDRegClass);
auto AsmTargetMIB =
MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg);
addStringImm(ST.getTargetTripleAsStr(), AsmTargetMIB);
@@ -644,7 +651,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
// define vendor specific assembly instructions string
Register AsmReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(AsmReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(AsmReg, &SPIRV::iIDRegClass);
auto AsmMIB = MIRBuilder.buildInstr(SPIRV::OpAsmINTEL)
.addDef(AsmReg)
.addUse(GR->getSPIRVTypeID(RetType))
@@ -687,7 +694,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
}
if (!DefReg.isValid()) {
DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(DefReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(DefReg, &SPIRV::iIDRegClass);
SPIRVType *VoidType = GR->getOrCreateSPIRVType(
Type::getVoidTy(MF.getFunction().getContext()), MIRBuilder);
GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
index e81d9695640468..52286c4f5cc11e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
@@ -10,4 +10,4 @@
// as InstructionSelector RegClass checking code relies on them
def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
-def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64]>;
+def IDRegBank : RegisterBank<"IDBank", [ID]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
index 17f6ba59cc5de0..936ad8e684b3e2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
@@ -39,8 +39,8 @@ let Namespace = "SPIRV" in {
def vpID320 : Register<"vpID320">;
def vpID640 : Register<"vpID640">;
- def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
- def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
+ def iID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
+ def iID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>;
def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
@@ -50,6 +50,12 @@ let Namespace = "SPIRV" in {
def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>;
def vpID64 : RegisterClass<"SPIRV", [v2p64], 32, (add vpID640)>;
+ def ID : RegisterClass<
+ "SPIRV",
+ [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
+ 32,
+ (add iID, iID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64)>;
+
def ANYID : RegisterClass<
"SPIRV",
[i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
diff --git a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll
index 7af5876a023e5b..f034f293dc6a99 100644
--- a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll
+++ b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#image1d_t:]] = OpTypeImage
; CHECK: %[[#sampler_t:]] = OpTypeSampler
diff --git a/llvm/test/CodeGen/SPIRV/atomicrmw.ll b/llvm/test/CodeGen/SPIRV/atomicrmw.ll
index 81484771575367..5f95a974ba671a 100644
--- a/llvm/test/CodeGen/SPIRV/atomicrmw.ll
+++ b/llvm/test/CodeGen/SPIRV/atomicrmw.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#Int:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}}
diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types.ll b/llvm/test/CodeGen/SPIRV/basic_int_types.ll
index 6bfc99025ccba5..bb664568ed842f 100644
--- a/llvm/test/CodeGen/SPIRV/basic_int_types.ll
+++ b/llvm/test/CodeGen/SPIRV/basic_int_types.ll
@@ -1,8 +1,12 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
define void @main() {
entry:
; CHECK-DAG: %[[#short:]] = OpTypeInt 16 0
diff --git a/llvm/test/CodeGen/SPIRV/empty.ll b/llvm/test/CodeGen/SPIRV/empty.ll
index 390ab329aea33b..29af913a0daee0 100644
--- a/llvm/test/CodeGen/SPIRV/empty.ll
+++ b/llvm/test/CodeGen/SPIRV/empty.ll
@@ -1,4 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpCapability Addresses
diff --git a/llvm/test/CodeGen/SPIRV/event-zero-const.ll b/llvm/test/CodeGen/SPIRV/event-zero-const.ll
index b40456d233f12f..f3f20a0fb2f41a 100644
--- a/llvm/test/CodeGen/SPIRV/event-zero-const.ll
+++ b/llvm/test/CodeGen/SPIRV/event-zero-const.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#LongTy:]] = OpTypeInt 64 0
diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll
index 82c1ec7dc916cf..251d870801c3cd 100644
--- a/llvm/test/CodeGen/SPIRV/expect.ll
+++ b/llvm/test/CodeGen/SPIRV/expect.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s
-; RUN: llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s
-; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s
-; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s
+; RUN: llc -verify-machineinstrs -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s
+; RUN: llc -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s
+; RUN: llc -verify-machineinstrs -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s
+; RUN: llc -verify-machineinstrs -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s
; EXT: OpCapability ExpectAssumeKHR
; EXT-NEXT: OpExtension "SPV_KHR_expect_assume"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
index e7b66798d3b340..14035a68c81aa4 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_add
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
index 3fd5bd65853f7d..d34811496e5a15 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_add
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
index 2f536dc53843c1..7da99411ae5306 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
@@ -1,7 +1,7 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR1
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR2
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add %s -o - | FileCheck %s
; CHECK-ERROR1: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_add
; CHECK-ERROR2: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float16_add
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
index 7654c3618fd48f..a2d0a594c861d2 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_min_max
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
index 8a359900282231..896b7acc1c87b2 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_min_max
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
index 45baaa8e9749a5..b3f48711707a14 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_EXT_shader_atomic_float_min_max %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: The atomic float instruction requires the following SPIR-V extension: SPV_EXT_shader_atomic_float_min_max
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll
index 359f6d1c0f8e53..5c3716602e5c07 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll
@@ -1,6 +1,6 @@
; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_cache_controls
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: Capability CacheControlsINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
index 986d88da418328..e963e3035be4d7 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
@@ -1,8 +1,9 @@
; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_usm_storage_classes/intel_usm_addrspaces.ll
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_usm_storage_classes %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-EXT
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_usm_storage_classes %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-EXT
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_usm_storage_classes %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-WITHOUT
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-WITHOUT
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-: Capability USMStorageClassesINTEL
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
index 8c5410aa54a433..7c40eed8465a1d 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; Make sure spirv operation function calls for all are generated.
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
index 7a74a335a659d4..54f5b7774b579e 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; Make sure spirv operation function calls for any are generated.
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
index b854412b6ec12a..1be8eb7e651661 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 0
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
index 1ccbd5a61067d8..8c5c036351d977 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
index 18c39ac9398797..a53bd8e53205ef 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll b/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
index 31cd8bd459297a..d075007777ddfe 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --translator-compatibility-mode -o - | FileCheck %s --check-prefix=CHECK-COMPAT
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s --translator-compatibility-mode -o - | FileCheck %s --check-prefix=CHECK-COMPAT
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s --translator-compatibility-mode -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
diff --git a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll
index f00c25a949b1e2..87df0aeb84d7da 100644
--- a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll
+++ b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll
@@ -1,4 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpDecorate %[[#ID:]] LinkageAttributes "imageSampler" Export
; CHECK: %[[#ID]] = OpVariable %[[#]] UniformConstant %[[#]]
diff --git a/llvm/test/CodeGen/SPIRV/literals.ll b/llvm/test/CodeGen/SPIRV/literals.ll
index d99ec36537d10f..4109bb6de56110 100644
--- a/llvm/test/CodeGen/SPIRV/literals.ll
+++ b/llvm/test/CodeGen/SPIRV/literals.ll
@@ -1,6 +1,11 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#F32:]] = OpTypeFloat 32
; CHECK: %[[#F64:]] = OpTypeFloat 64
diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
index 44b11f3ddb2731..f2f97f56263f95 100644
--- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
+++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
@@ -1,14 +1,18 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#type_int32:]] = OpTypeInt 32 0
-; CHECK-SPIRV-DAG: %[[#type_int64:]] = OpTypeInt 64 0
-; CHECK-SPIRV: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
-; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1
-; CHECK-SPIRV: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
-; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
-; CHECK-SPIRV: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
+; CHECK-DAG: %[[#type_int32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#type_int64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#type_int32]] 1
+; CHECK-DAG: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
+; CHECK-DAG: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+
+; CHECK: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
+; CHECK: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
define void @foo(i64* %arg) {
entry:
diff --git a/llvm/test/CodeGen/SPIRV/opencl/image.ll b/llvm/test/CodeGen/SPIRV/opencl/image.ll
index d87bb89fd2a6c2..b1150cfb2ff714 100644
--- a/llvm/test/CodeGen/SPIRV/opencl/image.ll
+++ b/llvm/test/CodeGen/SPIRV/opencl/image.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
;; FIXME: Write tests to ensure invalid usage of image are rejected, such as:
diff --git a/llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll b/llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
index ebc3fbfb10d17d..c2738229aa4d73 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
@@ -3,10 +3,10 @@
; 32- and 64-bits platforms. The test is successful if it doesn't crash and generate valid
; SPIR-V code for both 32 and 64 bits targets.
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV64
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV64
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV32
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV32
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV64-DAG: %[[#IntTy:]] = OpTypeInt 64 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
index e6130cedf68000..fefac863a6436e 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[#Char:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
index 989a724469c390..c4e810c6f3a595 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
@@ -1,4 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; CHECK-SPIRV-DAG: %[[#RetID:]] = OpImageSampleExplicitLod %[[#RetType:]] %[[#]] %[[#]] Lod %[[#]]
; CHECK-SPIRV-DAG: %[[#RetType]] = OpTypeVector %[[#]] 4
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll
index 30ef614bfa46d6..4e9ebec6bc9bed 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: %[[#VOID_TY:]] = OpTypeVoid
; CHECK-SPIRV: %[[#IMG2D_WO_TY:]] = OpTypeImage %[[#VOID_TY]] 2D 0 0 0 0 Unknown WriteOnly
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
index cb41aad2a0c5fa..37ab201b81a720 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
@@ -1,23 +1,23 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: OpName %[[#v:]] "v"
-; CHECK-SPIRV: OpName %[[#index:]] "index"
-; CHECK-SPIRV: OpName %[[#res:]] "res"
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#int16:]] = OpTypeInt 16
-; CHECK-SPIRV-DAG: %[[#int32:]] = OpTypeInt 32
-; CHECK-SPIRV-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
-
-; CHECK-SPIRV: %[[#undef:]] = OpUndef %[[#int16_2]]
-
-; CHECK-SPIRV-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
-; CHECK-SPIRV-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
-; CHECK-SPIRV-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
-; CHECK-SPIRV-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
-
-; CHECK-SPIRV: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
-; CHECK-SPIRV: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
-; CHECK-SPIRV: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
+; CHECK: OpName %[[#v:]] "v"
+; CHECK: OpName %[[#index:]] "index"
+; CHECK: OpName %[[#res:]] "res"
+; CHECK-DAG: %[[#int16:]] = OpTypeInt 16
+; CHECK-DAG: %[[#int32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
+; CHECK-DAG: %[[#undef:]] = OpUndef %[[#int16_2]]
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
+; CHECK-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
+; CHECK-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
+; CHECK-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
+; CHECK: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
+; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
+; CHECK: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
define spir_kernel void @test(<2 x i16>* nocapture %out, i16 %v, i32 %index) {
entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll
index 96e1d518a2d51c..e4c7bdb9e9c86c 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
;; constant sampler_t constSampl = CLK_FILTER_LINEAR;
;;
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll
index d7e87c05340d14..8b326e265502df 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll
@@ -18,7 +18,10 @@
;; ) {
;; }
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpCapability Sampled1D
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
index af76c0e96f9f49..d84fd492a86a87 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
@@ -8,6 +8,13 @@
; CHECK-SPIRV: OpName %[[#r5:]] "r5"
; CHECK-SPIRV: OpName %[[#r6:]] "r6"
; CHECK-SPIRV: OpName %[[#r7:]] "r7"
+; CHECK-SPIRV: OpName %[[#r1d:]] "r1"
+; CHECK-SPIRV: OpName %[[#r2d:]] "r2"
+; CHECK-SPIRV: OpName %[[#r3d:]] "r3"
+; CHECK-SPIRV: OpName %[[#r4d:]] "r4"
+; CHECK-SPIRV: OpName %[[#r5d:]] "r5"
+; CHECK-SPIRV: OpName %[[#r6d:]] "r6"
+; CHECK-SPIRV: OpName %[[#r7d:]] "r7"
; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
@@ -15,7 +22,9 @@
; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
-; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
+
; CHECK-SPIRV: %[[#r1]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r2]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r3]] = OpFAdd %[[#float]]
@@ -23,8 +32,7 @@
; CHECK-SPIRV: %[[#r5]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r6]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r7]] = OpFAdd %[[#float]]
-
-define spir_kernel void @testFAdd(float %a, float %b) {
+define spir_kernel void @testFAdd_float(float %a, float %b) {
entry:
%r1 = fadd float %a, %b
%r2 = fadd nnan float %a, %b
@@ -35,3 +43,22 @@ entry:
%r7 = fadd nnan ninf float %a, %b
ret void
}
+
+; CHECK-SPIRV: %[[#r1d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r2d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r3d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r4d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r5d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r6d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r7d]] = OpFAdd %[[#double]]
+define spir_kernel void @testFAdd_double(double %a, double %b) {
+entry:
+ %r1 = fadd double %a, %b
+ %r2 = fadd nnan double %a, %b
+ %r3 = fadd ninf double %a, %b
+ %r4 = fadd nsz double %a, %b
+ %r5 = fadd arcp double %a, %b
+ %r6 = fadd fast double %a, %b
+ %r7 = fadd nnan ninf double %a, %b
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll b/llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll
index a40a61a8dc7d77..65795d23657c24 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[#int:]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll b/llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll
index bfc3f044993474..8ab85cbbce9393 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpCapability ImageReadWrite
; CHECK-SPIRV-DAG: OpCapability LiteralSampler
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
index d44e32141db75b..790bf406ff531b 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpTypeInt 16
; CHECK: OpIAdd
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
index 04fb39118034c8..74dbaab63e03dc 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-32
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-32
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-64-DAG: %[[#i64:]] = OpTypeInt 64 0
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll
index f8db0ba2c1cd4e..8d99a0c6cd1ce9 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll
@@ -1,6 +1,10 @@
;; Test SPIR-V opaque types
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpCapability Float16
; CHECK-SPIRV-DAG: OpCapability ImageReadWrite
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll
index f605d0c42d34f7..1ba91a2efb6a01 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll
@@ -179,7 +179,8 @@
;; dst[8] = sub_group_scan_exclusive_max(v);
;; }
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[#char:]] = OpTypeInt 8 0
; CHECK-SPIRV-DAG: %[[#short:]] = OpTypeInt 16 0
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll
index 370e63e9b5c91a..b4099849934a17 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll
@@ -79,7 +79,8 @@
;; dst[1] = sub_group_shuffle_xor( v, 0 );
;; }
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffle
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll
index af2bc9b1c77cf5..f71d5e42330c94 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll
@@ -79,7 +79,8 @@
;; dst[1] = sub_group_shuffle_down( v, 0 );
;; }
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffleRelative
diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
index 32dc258d85554f..3dda3ff8c3c661 100644
--- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll
+++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#BOOL:]] = OpTypeBool
diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
index d2cd4ea8cafc36..f72334bd7752e7 100644
--- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll
+++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
@@ -1,5 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0
; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123
diff --git a/llvm/test/CodeGen/SPIRV/var-uniform-const.ll b/llvm/test/CodeGen/SPIRV/var-uniform-const.ll
index 6f7c91eb09e90b..b782f24cb9e906 100644
--- a/llvm/test/CodeGen/SPIRV/var-uniform-const.ll
+++ b/llvm/test/CodeGen/SPIRV/var-uniform-const.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[#Char:]] = OpTypeInt 8 0
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