[llvm] [LLVM] [X86] Fix integer overflows in frame layout for huge frames (PR #101840)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 12 05:47:52 PDT 2024
================
@@ -945,11 +947,34 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
if (MI.getOperand(FIOperandNum+3).isImm()) {
- // Offset is a 32-bit integer.
- int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
- int Offset = FIOffset + Imm;
- assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
- "Requesting 64-bit offset in 32-bit immediate!");
+ int64_t Imm = MI.getOperand(FIOperandNum + 3).getImm();
+ int64_t Offset = FIOffset + Imm;
+ bool FitsIn32Bits = isInt<32>(Offset);
+ // If the offset will not fit in a 32-bit displacement,
+ // then for 64-bit targets, scavenge a register to hold it.
+ // Otherwise, for 32-bit targets, this is a bug!
+ if (Is64Bit && !FitsIn32Bits) {
+ assert(RS && "RegisterScavenger was NULL");
+ const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
+ DebugLoc DL = MI.getDebugLoc();
+
+ RS->enterBasicBlockEnd(MBB);
+ RS->backward(std::next(II));
+
+ Register ScratchReg =
+ RS->scavengeRegisterBackwards(X86::GR64RegClass, II, false, 0, true);
+ assert(ScratchReg != 0 && "scratch reg was 0");
+ RS->setRegUsed(ScratchReg);
+
+ BuildMI(MBB, II, DL, TII->get(X86::MOV64ri), ScratchReg).addImm(Offset);
+
+ MI.getOperand(FIOperandNum + 3).setImm(0);
+ MI.getOperand(FIOperandNum + 2).setReg(ScratchReg);
+
+ return false;
+ } else if (!Is64Bit) {
+ assert(FitsIn32Bits && "Requesting 64-bit offset in 32-bit immediate!");
----------------
arsenm wrote:
I'd just drop the assert and let the verifier take care of it then. Or at least fold the !Is64Bit into the assert condition instead of having if (x) assert();
https://github.com/llvm/llvm-project/pull/101840
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