[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[Sam Tebbs via llvm-commits]

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@@ -21237,6 +21279,32 @@ static SDValue performIntrinsicCombine(SDNode *N,
   switch (IID) {
   default:
     break;
+  case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc DL(N);
+
+    auto NarrowOp = N->getOperand(1);
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SamTebbs33 wrote:

Just realised I got a bit of the logic with `IsValidDotProduct` wrong. I'll fix that up in the next commit.

https://github.com/llvm/llvm-project/pull/101010