[llvm] [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (PR #101751)

[David Green via llvm-commits]

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@@ -244,8 +243,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
 ;
 ; ARM8-LABEL: test_srem_pow2_setne:
 ; ARM8:       @ %bb.0:
-; ARM8-NEXT:    sbfx r1, r0, #0, #6
-; ARM8-NEXT:    ubfx r1, r1, #9, #2
+; ARM8-NEXT:    lsl r1, r0, #26
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davemgreen wrote:

Considering these get optimized very differently by opt, and I don't see this coming up elsewhere I think it is OK. (I may look into it in the future to see if there is something we can do more generally to improve it).

https://github.com/llvm/llvm-project/pull/101751