[llvm] [LV]Enable max safe distance in predicated DataWithEVL vectorization mode. (PR #100755)

[via llvm-commits]

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@@ -100,6 +100,8 @@ static cl::opt<unsigned> MemoryCheckMergeThreshold(
 
 /// Maximum SIMD width.
 const unsigned VectorizerParams::MaxVectorWidth = 64;
+/// Maximum LMUL factor.
+const unsigned VectorizerParams::MaxVectorLMUL = 8;
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ayalz wrote:

AFAIU yes, stemming from RISCVV having 32 architected vector registers, which become 4 with LMUL = 8. According to https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc, LMUL can be 1, 2, 4, 8 and also 1/2, 1/4, 1/8.

https://github.com/llvm/llvm-project/pull/100755