[llvm] [Mips] ISel zext nneg the same as sext for Mips64. (PR #102852)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 11 23:25:49 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/102852
Fixes #62587.
>From 33c9e6f2e295add223bd44cfc8434474361572e3 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 11 Aug 2024 23:15:48 -0700
Subject: [PATCH] [Mips] ISel zext nneg the same as sext for Mips64.
Fixes #62587.
---
llvm/lib/Target/Mips/Mips64InstrInfo.td | 33 +++++++++++++++----------
llvm/test/CodeGen/Mips/bittest.ll | 31 +++++++++--------------
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index cb9a0d44a7a72b..b96ff61251aebd 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -837,13 +837,20 @@ def : MipsPat<(MipsExt (i32 (trunc GPR64:$src)), immZExt5:$pos, immZExt5:$size),
(EXTRACT_SUBREG (DEXT GPR64:$src, immZExt5:$pos, immZExt5:$size), sub_32)>,
ISA_MIPS3, GPR_64;
+def zext_nneg : PatFrag<(ops node:$src), (zext node:$src), [{
+ return N->getFlags().hasNonNeg();
+}]>;
+def sext_like : PatFrags<(ops node:$src),
+ [(zext_nneg node:$src),
+ (sext node:$src)]>;
+
// 32-to-64-bit extension
def : MipsPat<(i64 (anyext GPR32:$src)),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>,
ISA_MIPS3, GPR_64;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>,
ISA_MIPS3, GPR_64;
-def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3,
+def : MipsPat<(i64 (sext_like GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3,
GPR_64;
let AdditionalPredicates = [NotInMicroMips] in {
@@ -911,40 +918,40 @@ def : MipsPat<(atomic_store_64 GPR64:$v, addr:$a), (SD GPR64:$v, addr:$a)>,
// Patterns used for matching away redundant sign extensions.
// MIPS32 arithmetic instructions sign extend their result implicitly.
-def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))),
+def : MipsPat<(i64 (sext_like (i32 (add GPR32:$src, immSExt16:$imm16)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (add GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(ADDu GPR32:$src, GPR32:$src2), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (sub GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SUBu GPR32:$src, GPR32:$src2), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (mul GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS32_NOT_32R6_64R6;
-def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))),
+def : MipsPat<(i64 (sext_like (i32 (MipsMFHI ACC64:$src)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(PseudoMFHI ACC64:$src), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))),
+def : MipsPat<(i64 (sext_like (i32 (MipsMFLO ACC64:$src)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(PseudoMFLO ACC64:$src), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
+def : MipsPat<(i64 (sext_like (i32 (shl GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (shl GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SLLV GPR32:$src, GPR32:$src2), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
+def : MipsPat<(i64 (sext_like (i32 (srl GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (srl GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRLV GPR32:$src, GPR32:$src2), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
+def : MipsPat<(i64 (sext_like (i32 (sra GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
-def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))),
+def : MipsPat<(i64 (sext_like (i32 (sra GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRAV GPR32:$src, GPR32:$src2), sub_32)>;
diff --git a/llvm/test/CodeGen/Mips/bittest.ll b/llvm/test/CodeGen/Mips/bittest.ll
index 167140c83b0669..062c8002490f52 100644
--- a/llvm/test/CodeGen/Mips/bittest.ll
+++ b/llvm/test/CodeGen/Mips/bittest.ll
@@ -53,23 +53,22 @@ define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
; MIPS64: # %bb.0:
; MIPS64-NEXT: andi $1, $4, 1024
; MIPS64-NEXT: sltiu $1, $1, 1
-; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: dsrl $2, $1, 32
+; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_10_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: andi $1, $4, 1024
; MIPS64R2-NEXT: sltiu $1, $1, 1
; MIPS64R2-NEXT: jr $ra
-; MIPS64R2-NEXT: dext $2, $1, 0, 32
+; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_10_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: andi $1, $4, 1024
; MIPS64R6-NEXT: sltiu $1, $1, 1
; MIPS64R6-NEXT: jr $ra
-; MIPS64R6-NEXT: dext $2, $1, 0, 32
+; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_10_i32:
; MM32R3: # %bb.0:
@@ -111,23 +110,22 @@ define signext i32 @bittest_15_i32(i32 signext %a) nounwind {
; MIPS64: # %bb.0:
; MIPS64-NEXT: andi $1, $4, 32768
; MIPS64-NEXT: sltiu $1, $1, 1
-; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: dsrl $2, $1, 32
+; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_15_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: andi $1, $4, 32768
; MIPS64R2-NEXT: sltiu $1, $1, 1
; MIPS64R2-NEXT: jr $ra
-; MIPS64R2-NEXT: dext $2, $1, 0, 32
+; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_15_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: andi $1, $4, 32768
; MIPS64R6-NEXT: sltiu $1, $1, 1
; MIPS64R6-NEXT: jr $ra
-; MIPS64R6-NEXT: dext $2, $1, 0, 32
+; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_15_i32:
; MM32R3: # %bb.0:
@@ -171,23 +169,22 @@ define signext i32 @bittest_16_i32(i32 signext %a) nounwind {
; MIPS64-NEXT: not $1, $4
; MIPS64-NEXT: srl $1, $1, 16
; MIPS64-NEXT: andi $1, $1, 1
-; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: dsrl $2, $1, 32
+; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_16_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: not $1, $4
; MIPS64R2-NEXT: ext $1, $1, 16, 1
; MIPS64R2-NEXT: jr $ra
-; MIPS64R2-NEXT: dext $2, $1, 0, 32
+; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_16_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: not $1, $4
; MIPS64R6-NEXT: ext $1, $1, 16, 1
; MIPS64R6-NEXT: jr $ra
-; MIPS64R6-NEXT: dext $2, $1, 0, 32
+; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_16_i32:
; MM32R3: # %bb.0:
@@ -228,24 +225,20 @@ define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; MIPS64-LABEL: bittest_31_i32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: not $1, $4
-; MIPS64-NEXT: srl $1, $1, 31
-; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: dsrl $2, $1, 32
+; MIPS64-NEXT: srl $2, $1, 31
;
; MIPS64R2-LABEL: bittest_31_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: not $1, $4
-; MIPS64R2-NEXT: srl $1, $1, 31
; MIPS64R2-NEXT: jr $ra
-; MIPS64R2-NEXT: dext $2, $1, 0, 32
+; MIPS64R2-NEXT: srl $2, $1, 31
;
; MIPS64R6-LABEL: bittest_31_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: not $1, $4
-; MIPS64R6-NEXT: srl $1, $1, 31
; MIPS64R6-NEXT: jr $ra
-; MIPS64R6-NEXT: dext $2, $1, 0, 32
+; MIPS64R6-NEXT: srl $2, $1, 31
;
; MM32R3-LABEL: bittest_31_i32:
; MM32R3: # %bb.0:
More information about the llvm-commits
mailing list