[llvm] [RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (PR #102802)

[Craig Topper via llvm-commits]

================
@@ -1164,6 +1164,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     }
 
     unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
+    if (Subtarget->hasVendorXTHeadBb() && TrailingOnes > ShAmt) {
----------------
topperc wrote:

TrailingOnes > ShAmt is always true here, it was checked on line 1142.

https://github.com/llvm/llvm-project/pull/102802