[llvm] [LegalizeTypes] Reuse Op1 and Op2 variables to hold promoted values in PromoteIntRes_ADDSUBSHLSAT. NFC (PR #102840)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

We don't need the original values after we promote them.

---
Full diff: https://github.com/llvm/llvm-project/pull/102840.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+12-17) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 3635bc7a96580..27c8d7460db69 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1059,25 +1059,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
   bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
 
   // FIXME: We need vp-aware PromotedInteger functions.
-  SDValue Op1Promoted, Op2Promoted;
   if (IsShift) {
-    Op1Promoted = GetPromotedInteger(Op1);
-    Op2Promoted = ZExtPromotedInteger(Op2);
+    Op1 = GetPromotedInteger(Op1);
+    Op2 = ZExtPromotedInteger(Op2);
   } else if (Opcode == ISD::UADDSAT) {
-    Op1Promoted = ZExtPromotedInteger(Op1);
-    Op2Promoted = ZExtPromotedInteger(Op2);
+    Op1 = ZExtPromotedInteger(Op1);
+    Op2 = ZExtPromotedInteger(Op2);
   } else {
-    Op1Promoted = SExtPromotedInteger(Op1);
-    Op2Promoted = SExtPromotedInteger(Op2);
+    Op1 = SExtPromotedInteger(Op1);
+    Op2 = SExtPromotedInteger(Op2);
   }
-  EVT PromotedType = Op1Promoted.getValueType();
+  EVT PromotedType = Op1.getValueType();
   unsigned NewBits = PromotedType.getScalarSizeInBits();
 
   if (Opcode == ISD::UADDSAT) {
     APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
     SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
     SDValue Add =
-        matcher.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
+        matcher.getNode(ISD::ADD, dl, PromotedType, Op1, Op2);
     return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
   }
 
@@ -1102,14 +1101,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
     unsigned SHLAmount = NewBits - OldBits;
     SDValue ShiftAmount =
         DAG.getShiftAmountConstant(SHLAmount, PromotedType, dl);
-    Op1Promoted =
-        DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
+    Op1 = DAG.getNode(ISD::SHL, dl, PromotedType, Op1, ShiftAmount);
     if (!IsShift)
-      Op2Promoted =
-          matcher.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
+      Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
 
-    SDValue Result =
-        matcher.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
+    SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
     return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
   }
 
@@ -1118,8 +1114,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
   APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
   SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
   SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
-  SDValue Result =
-      matcher.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
+  SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
   Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
   Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
   return Result;

``````````

</details>


https://github.com/llvm/llvm-project/pull/102840