[llvm] [Xtensa] Implement lowering Mul/Div/Shift operations. (PR #99981)

Sergei Barannikov via llvm-commits llvm-commits at lists.llvm.org
Sun Aug 11 17:10:17 PDT 2024


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@@ -125,12 +125,75 @@ FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
 
 void XtensaDAGToDAGISel::Select(SDNode *Node) {
   SDLoc DL(Node);
+  EVT VT = Node->getValueType(0);
 
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
     Node->setNodeId(-1);
     return;
   }
 
+  switch (Node->getOpcode()) {
+  case ISD::SHL: {
+    SDValue N0 = Node->getOperand(0);
+    SDValue N1 = Node->getOperand(1);
+    if (!isa<ConstantSDNode>(N1)) {
+      SDNode *SSL = CurDAG->getMachineNode(Xtensa::SSL, DL, MVT::Glue, N1);
+      SDNode *SLL =
+          CurDAG->getMachineNode(Xtensa::SLL, DL, VT, N0, SDValue(SSL, 0));
+      ReplaceNode(Node, SLL);
+      return;
+    }
+    break;
+  }
+  case ISD::SRL: {
+    SDValue N0 = Node->getOperand(0);
+    SDValue N1 = Node->getOperand(1);
+    auto *C = dyn_cast<ConstantSDNode>(N1);
+    // If C is constant in range [0..15] then we can generate SRLI
+    // instruction using pattern matching, otherwise generate SRL
----------------
s-barannikov wrote:

This was a question :)

https://github.com/llvm/llvm-project/pull/99981


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