[llvm] [LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to promote operands for USUBSAT. (PR #102781)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 10 18:38:05 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/102781
It doesn't matter which extend we use to promote the operands. Use whatever is the most efficient.
The custom handler for RISC-V was using SIGN_EXTEND when the Zbb extension is enabled so we no longer need that.
>From 3cff45d562f8a182e85d9eda7e77236f33060bd3 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 10 Aug 2024 18:25:57 -0700
Subject: [PATCH] [LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to
promote operands for USUBSAT.
I doesn't matter which extend we use to promote the operands. Use
whatever is the most efficient.
The custom handler for RISC-V was using SIGN_EXTEND when the Zbb
extension is enabled so we no longer need that.
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 17 ++++++++++-------
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 ++++---
llvm/test/CodeGen/RISCV/usub_sat_plus.ll | 2 +-
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 79ff33aa705ef3..3635bc7a965804 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1045,9 +1045,17 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
SDValue Op1 = N->getOperand(0);
SDValue Op2 = N->getOperand(1);
MatchContextClass matcher(DAG, TLI, N);
- unsigned OldBits = Op1.getScalarValueSizeInBits();
unsigned Opcode = matcher.getRootBaseOpcode();
+ unsigned OldBits = Op1.getScalarValueSizeInBits();
+
+ // USUBSAT can always be promoted as long as we have zero/sign-extended the
+ // args.
+ if (Opcode == ISD::USUBSAT) {
+ SExtOrZExtPromotedOperands(Op1, Op2);
+ return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
+ }
+
bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
// FIXME: We need vp-aware PromotedInteger functions.
@@ -1055,7 +1063,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
if (IsShift) {
Op1Promoted = GetPromotedInteger(Op1);
Op2Promoted = ZExtPromotedInteger(Op2);
- } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
+ } else if (Opcode == ISD::UADDSAT) {
Op1Promoted = ZExtPromotedInteger(Op1);
Op2Promoted = ZExtPromotedInteger(Op2);
} else {
@@ -1073,11 +1081,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
}
- // USUBSAT can always be promoted as long as we have zero-extended the args.
- if (Opcode == ISD::USUBSAT)
- return matcher.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
- Op2Promoted);
-
// Shift cannot use a min/max expansion, we can't detect overflow if all of
// the bits have been shifted out.
if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d6d96dd4edf8ad..872c288f5ad8cd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -268,10 +268,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::LOAD, MVT::i32, Custom);
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
MVT::i32, Custom);
- setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
- MVT::i32, Custom);
+ setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT}, MVT::i32,
+ Custom);
if (!Subtarget.hasStdExtZbb())
- setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
+ setOperationAction({ISD::SADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, MVT::i32,
+ Custom);
setOperationAction(ISD::SADDO, MVT::i32, Custom);
}
if (!Subtarget.hasStdExtZmmul()) {
diff --git a/llvm/test/CodeGen/RISCV/usub_sat_plus.ll b/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
index 393466d89e8ca9..c76a53468f7689 100644
--- a/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
@@ -39,8 +39,8 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
;
; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0:
-; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: sext.w a0, a0
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: ret
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