[llvm] [RISCV][MC] Remove register substitutions in `RISCVAsmPrinter` (PR #102728)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 9 23:46:42 PDT 2024
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/102728
Since we have the name for those registers, the `AsmPrinter` and
`AsmParser` can recognize them correctly, we don't need to substitute
them manually.
>From 59ea0cee39f59e0e0afe21ea4093a1df2599047e Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 9 Aug 2024 23:36:54 -0700
Subject: [PATCH] [RISCV][MC] Remove register substitutions in
`RISCVAsmPrinter`
Since we have the name for those registers, the `AsmPrinter` and
`AsmParser` can recognize them correctly, we don't need to substitute
them manually.
---
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 14 +-
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 48 +++----
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 60 ++++-----
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 24 ++--
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 60 ++++-----
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 96 +++++++-------
.../CodeGen/RISCV/rvv/double-round-conv.ll | 48 +++----
.../RISCV/rvv/fceil-constrained-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll | 18 +--
.../RISCV/rvv/ffloor-constrained-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll | 18 +--
.../RISCV/rvv/fixed-vectors-ceil-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 120 +++++++++---------
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 20 +--
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 120 +++++++++---------
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 20 +--
.../fixed-vectors-fceil-constrained-sdnode.ll | 12 +-
...fixed-vectors-ffloor-constrained-sdnode.ll | 12 +-
.../RISCV/rvv/fixed-vectors-floor-vp.ll | 44 +++----
...d-vectors-fnearbyint-constrained-sdnode.ll | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fp.ll | 8 +-
...fixed-vectors-fround-constrained-sdnode.ll | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fround.ll | 18 +--
...d-vectors-froundeven-constrained-sdnode.ll | 12 +-
.../RISCV/rvv/fixed-vectors-froundeven.ll | 18 +--
.../RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll | 40 +++---
...fixed-vectors-ftrunc-constrained-sdnode.ll | 12 +-
.../RISCV/rvv/fixed-vectors-nearbyint-vp.ll | 36 +++---
.../RISCV/rvv/fixed-vectors-rint-vp.ll | 36 +++---
.../RISCV/rvv/fixed-vectors-round-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-vfabs-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-vfneg-vp.ll | 44 +++----
.../RISCV/rvv/fixed-vectors-vxor-vp.ll | 24 ++--
.../CodeGen/RISCV/rvv/float-round-conv.ll | 24 ++--
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 48 +++----
.../rvv/fnearbyint-constrained-sdnode.ll | 18 +--
.../CodeGen/RISCV/rvv/fnearbyint-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll | 18 +--
.../RISCV/rvv/fround-constrained-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll | 18 +--
.../rvv/froundeven-constrained-sdnode.ll | 18 +--
.../CodeGen/RISCV/rvv/froundeven-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 60 ++++-----
.../RISCV/rvv/ftrunc-constrained-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 68 +++++-----
llvm/test/CodeGen/RISCV/rvv/rint-vp.ll | 68 +++++-----
llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 68 +++++-----
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 68 +++++-----
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 68 +++++-----
llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll | 48 +++----
llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll | 48 +++----
llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll | 28 ++--
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 68 +++++-----
.../CodeGen/RISCV/rvv/vfcopysign-sdnode.ll | 26 ++--
.../RISCV/rvv/vfmsub-constrained-sdnode.ll | 20 +--
llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll | 28 ++--
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 68 +++++-----
.../RISCV/rvv/vfnmadd-constrained-sdnode.ll | 38 +++---
.../RISCV/rvv/vfnmsub-constrained-sdnode.ll | 18 +--
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll | 24 ++--
llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 52 ++++----
64 files changed, 1175 insertions(+), 1187 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 93677433c04405..64e24394d66d9c 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -996,19 +996,7 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
case MachineOperand::MO_Register: {
Register Reg = MO.getReg();
- if (RISCV::VRM2RegClass.contains(Reg) ||
- RISCV::VRM4RegClass.contains(Reg) ||
- RISCV::VRM8RegClass.contains(Reg)) {
- Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
- assert(Reg && "Subregister does not exist");
- } else if (RISCV::FPR16RegClass.contains(Reg)) {
- Reg =
- TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
- assert(Reg && "Subregister does not exist");
- } else if (RISCV::FPR64RegClass.contains(Reg)) {
- Reg = TRI->getSubReg(Reg, RISCV::sub_32);
- assert(Reg && "Superregister does not exist");
- } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
+ if (RISCV::VRN2M1RegClass.contains(Reg) ||
RISCV::VRN2M2RegClass.contains(Reg) ||
RISCV::VRN2M4RegClass.contains(Reg) ||
RISCV::VRN3M1RegClass.contains(Reg) ||
diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
index dec67721514de6..838b86a33f3adb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
@@ -139,7 +139,7 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -161,7 +161,7 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16_unmasked(<vscale x 8 x half> %va,
; CHECK-NEXT: lui a1, %hi(.LCPI7_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -183,7 +183,7 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; CHECK-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -205,7 +205,7 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16_unmasked(<vscale x 16 x half> %
; CHECK-NEXT: lui a1, %hi(.LCPI9_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -227,7 +227,7 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; CHECK-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -249,7 +249,7 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; CHECK-NEXT: lui a1, %hi(.LCPI11_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -353,7 +353,7 @@ define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscal
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -375,7 +375,7 @@ define <vscale x 4 x float> @vp_ceil_vv_nxv4f32_unmasked(<vscale x 4 x float> %v
; CHECK-LABEL: vp_ceil_vv_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -397,7 +397,7 @@ define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscal
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -419,7 +419,7 @@ define <vscale x 8 x float> @vp_ceil_vv_nxv8f32_unmasked(<vscale x 8 x float> %v
; CHECK-LABEL: vp_ceil_vv_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -441,7 +441,7 @@ define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -463,7 +463,7 @@ define <vscale x 16 x float> @vp_ceil_vv_nxv16f32_unmasked(<vscale x 16 x float>
; CHECK-LABEL: vp_ceil_vv_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -529,7 +529,7 @@ define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vsc
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -551,7 +551,7 @@ define <vscale x 2 x double> @vp_ceil_vv_nxv2f64_unmasked(<vscale x 2 x double>
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -573,7 +573,7 @@ define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vsc
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -595,7 +595,7 @@ define <vscale x 4 x double> @vp_ceil_vv_nxv4f64_unmasked(<vscale x 4 x double>
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -617,7 +617,7 @@ define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vsc
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -639,7 +639,7 @@ define <vscale x 7 x double> @vp_ceil_vv_nxv7f64_unmasked(<vscale x 7 x double>
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -661,7 +661,7 @@ define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vsc
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -683,7 +683,7 @@ define <vscale x 8 x double> @vp_ceil_vv_nxv8f64_unmasked(<vscale x 8 x double>
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -721,7 +721,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a2, 3
@@ -742,7 +742,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -773,7 +773,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a2, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -786,7 +786,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
index d51f5eacd7d91a..c87088a65992fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
@@ -270,7 +270,7 @@ define <vscale x 16 x i8> @ctlz_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: li a0, 85
; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
@@ -333,7 +333,7 @@ define <vscale x 32 x i8> @ctlz_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0
@@ -368,7 +368,7 @@ define <vscale x 64 x i8> @ctlz_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0
@@ -603,7 +603,7 @@ define <vscale x 8 x i16> @ctlz_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 8
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -669,7 +669,7 @@ define <vscale x 16 x i16> @ctlz_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 8
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -735,7 +735,7 @@ define <vscale x 32 x i16> @ctlz_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -925,7 +925,7 @@ define <vscale x 4 x i32> @ctlz_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -997,7 +997,7 @@ define <vscale x 8 x i32> @ctlz_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -1069,7 +1069,7 @@ define <vscale x 16 x i32> @ctlz_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v16
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v16
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -1285,7 +1285,7 @@ define <vscale x 2 x i64> @ctlz_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v10, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v10
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -1337,7 +1337,7 @@ define <vscale x 2 x i64> @ctlz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v10, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v10
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
@@ -1425,7 +1425,7 @@ define <vscale x 4 x i64> @ctlz_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v12, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v12
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v12, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -1477,7 +1477,7 @@ define <vscale x 4 x i64> @ctlz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v12, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v12
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v12, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
@@ -1565,7 +1565,7 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v16, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v16
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v16, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -1617,7 +1617,7 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v16, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v16
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v16, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
@@ -1930,7 +1930,7 @@ define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: li a0, 85
; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
@@ -1988,7 +1988,7 @@ define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0
@@ -2022,7 +2022,7 @@ define <vscale x 64 x i8> @ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0
@@ -2241,7 +2241,7 @@ define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 8
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -2302,7 +2302,7 @@ define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 8
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -2363,7 +2363,7 @@ define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -2542,7 +2542,7 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v10
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -2609,7 +2609,7 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v12
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -2676,7 +2676,7 @@ define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v16
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 16
; CHECK-ZVE64X-NEXT: vor.vv v8, v8, v16
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
@@ -2881,7 +2881,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v10, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v10
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -2933,7 +2933,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v10, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v10
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
@@ -3015,7 +3015,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v12, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v12
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v12, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -3067,7 +3067,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v12, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v12
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v12, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
@@ -3149,7 +3149,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: vsrl.vx v16, v8, a0
; RV32I-NEXT: vor.vv v8, v8, v16
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v16, v8, 1
; RV32I-NEXT: lui a0, 349525
; RV32I-NEXT: addi a0, a0, 1365
@@ -3201,7 +3201,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: vsrl.vx v16, v8, a0
; RV64I-NEXT: vor.vv v8, v8, v16
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v16, v8, 1
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: addiw a0, a0, 1365
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index 58882525e55c4c..1af280b70b2442 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -285,7 +285,7 @@ define <vscale x 32 x i8> @vp_ctlz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
@@ -319,7 +319,7 @@ define <vscale x 32 x i8> @vp_ctlz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0
@@ -355,7 +355,7 @@ define <vscale x 64 x i8> @vp_ctlz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
@@ -389,7 +389,7 @@ define <vscale x 64 x i8> @vp_ctlz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0
@@ -662,7 +662,7 @@ define <vscale x 32 x i16> @vp_ctlz_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -705,7 +705,7 @@ define <vscale x 32 x i16> @vp_ctlz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -1594,7 +1594,7 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
@@ -1628,7 +1628,7 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0
@@ -1663,7 +1663,7 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
@@ -1697,7 +1697,7 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0
@@ -1944,7 +1944,7 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -1987,7 +1987,7 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v16
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 3bddcf798f66bf..19b8ee5b64a6ae 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -278,7 +278,7 @@ define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: li a0, 85
@@ -344,7 +344,7 @@ define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
@@ -376,7 +376,7 @@ define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
@@ -609,7 +609,7 @@ define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
@@ -676,7 +676,7 @@ define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
@@ -743,7 +743,7 @@ define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -924,7 +924,7 @@ define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -995,7 +995,7 @@ define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -1066,7 +1066,7 @@ define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -1264,7 +1264,7 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32I-NEXT: vsub.vx v10, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v10
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -1306,7 +1306,7 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64I-NEXT: vsub.vx v10, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v10
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a0, 349525
@@ -1390,7 +1390,7 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32I-NEXT: vsub.vx v12, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v12
; RV32I-NEXT: vsrl.vi v12, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -1432,7 +1432,7 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64I-NEXT: vsub.vx v12, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v12
; RV64I-NEXT: vsrl.vi v12, v8, 1
; RV64I-NEXT: lui a0, 349525
@@ -1516,7 +1516,7 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32I-NEXT: vsub.vx v16, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v16
; RV32I-NEXT: vsrl.vi v16, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -1558,7 +1558,7 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64I-NEXT: vsub.vx v16, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v16
; RV64I-NEXT: vsrl.vi v16, v8, 1
; RV64I-NEXT: lui a0, 349525
@@ -1886,7 +1886,7 @@ define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: li a0, 85
@@ -1947,7 +1947,7 @@ define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
@@ -1978,7 +1978,7 @@ define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
@@ -2189,7 +2189,7 @@ define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
@@ -2249,7 +2249,7 @@ define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 5
@@ -2309,7 +2309,7 @@ define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a0
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -2475,7 +2475,7 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -2539,7 +2539,7 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -2603,7 +2603,7 @@ define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: li a0, 1
; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
-; CHECK-ZVE64X-NEXT: vnot.v v8, v8
+; CHECK-ZVE64X-NEXT: vxor.vi v8, v8, -1
; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
; CHECK-ZVE64X-NEXT: lui a0, 349525
@@ -2786,7 +2786,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32I-NEXT: vsub.vx v10, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v10
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -2828,7 +2828,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64I-NEXT: vsub.vx v10, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v10
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a0, 349525
@@ -2904,7 +2904,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32I-NEXT: vsub.vx v12, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v12
; RV32I-NEXT: vsrl.vi v12, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -2946,7 +2946,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64I-NEXT: vsub.vx v12, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v12
; RV64I-NEXT: vsrl.vi v12, v8, 1
; RV64I-NEXT: lui a0, 349525
@@ -3022,7 +3022,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32I-NEXT: vsub.vx v16, v8, a0
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v16
; RV32I-NEXT: vsrl.vi v16, v8, 1
; RV32I-NEXT: lui a0, 349525
@@ -3064,7 +3064,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64I-NEXT: vsub.vx v16, v8, a0
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v16
; RV64I-NEXT: vsrl.vi v16, v8, 1
; RV64I-NEXT: lui a0, 349525
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index 0ef0a431dabc43..933eb7c6ab5a31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -272,7 +272,7 @@ define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
@@ -303,7 +303,7 @@ define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: li a0, 85
@@ -336,7 +336,7 @@ define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
@@ -367,7 +367,7 @@ define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
@@ -400,7 +400,7 @@ define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
@@ -431,7 +431,7 @@ define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
@@ -698,7 +698,7 @@ define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -736,7 +736,7 @@ define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -776,7 +776,7 @@ define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -814,7 +814,7 @@ define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -854,7 +854,7 @@ define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -892,7 +892,7 @@ define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -1092,7 +1092,7 @@ define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -1131,7 +1131,7 @@ define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -1172,7 +1172,7 @@ define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -1211,7 +1211,7 @@ define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -1252,7 +1252,7 @@ define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -1291,7 +1291,7 @@ define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -1514,7 +1514,7 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -1556,7 +1556,7 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v10, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1604,7 +1604,7 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -1646,7 +1646,7 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1696,7 +1696,7 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -1738,7 +1738,7 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v12, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1786,7 +1786,7 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -1828,7 +1828,7 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1878,7 +1878,7 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -1920,7 +1920,7 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1968,7 +1968,7 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -2010,7 +2010,7 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -2060,7 +2060,7 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -2102,7 +2102,7 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -2150,7 +2150,7 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -2192,7 +2192,7 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -2263,7 +2263,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a2, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vxor.vi v16, v16, -1, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 40
@@ -2385,7 +2385,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a2, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5
@@ -2511,7 +2511,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: li a2, 1
; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v8, v16, a2, v0.t
-; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vxor.vi v16, v16, -1, v0.t
; RV64-NEXT: vand.vv v16, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v8, v16, 1, v0.t
; RV64-NEXT: lui a3, 349525
@@ -2555,7 +2555,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a2, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: vand.vx v16, v16, a3, v0.t
@@ -2625,7 +2625,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a2
-; RV32-NEXT: vnot.v v16, v16
+; RV32-NEXT: vxor.vi v16, v16, -1
; RV32-NEXT: vand.vv v16, v16, v8
; RV32-NEXT: vsrl.vi v24, v16, 1
; RV32-NEXT: lui a4, 349525
@@ -2688,7 +2688,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v24, a2
-; RV32-NEXT: vnot.v v24, v24
+; RV32-NEXT: vxor.vi v24, v24, -1
; RV32-NEXT: vand.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: csrr a0, vlenb
@@ -2737,7 +2737,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
; RV64-NEXT: li a2, 1
; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v16, a2
-; RV64-NEXT: vnot.v v16, v16
+; RV64-NEXT: vxor.vi v16, v16, -1
; RV64-NEXT: vand.vv v16, v16, v24
; RV64-NEXT: vsrl.vi v24, v16, 1
; RV64-NEXT: lui a3, 349525
@@ -2774,7 +2774,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
; RV64-NEXT: .LBB47_2:
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v8, a2
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v24
; RV64-NEXT: vsrl.vi v24, v8, 1
; RV64-NEXT: vand.vx v24, v24, a3
@@ -3086,7 +3086,7 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
@@ -3117,7 +3117,7 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: li a0, 85
@@ -3149,7 +3149,7 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: li a0, 85
@@ -3180,7 +3180,7 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: li a0, 85
@@ -3442,7 +3442,7 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -3480,7 +3480,7 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: lui a0, 5
diff --git a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
index 8c63c2d4be8c1c..b0d5f7707c7130 100644
--- a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
@@ -258,7 +258,7 @@ define <vscale x 4 x i8> @trunc_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI8_0)
; RV32-NEXT: fld fa5, %lo(.LCPI8_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -277,7 +277,7 @@ define <vscale x 4 x i8> @trunc_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI8_0)
; RV64-NEXT: fld fa5, %lo(.LCPI8_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -301,7 +301,7 @@ define <vscale x 4 x i8> @trunc_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-NEXT: fld fa5, %lo(.LCPI9_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -320,7 +320,7 @@ define <vscale x 4 x i8> @trunc_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI9_0)
; RV64-NEXT: fld fa5, %lo(.LCPI9_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -344,7 +344,7 @@ define <vscale x 4 x i16> @trunc_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-NEXT: fld fa5, %lo(.LCPI10_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -361,7 +361,7 @@ define <vscale x 4 x i16> @trunc_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-NEXT: fld fa5, %lo(.LCPI10_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -383,7 +383,7 @@ define <vscale x 4 x i16> @trunc_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -400,7 +400,7 @@ define <vscale x 4 x i16> @trunc_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI11_0)
; RV64-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -774,7 +774,7 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI24_0)
; RV32-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -795,7 +795,7 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI24_0)
; RV64-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -821,7 +821,7 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI25_0)
; RV32-NEXT: fld fa5, %lo(.LCPI25_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -842,7 +842,7 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI25_0)
; RV64-NEXT: fld fa5, %lo(.LCPI25_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -868,7 +868,7 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI26_0)
; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -887,7 +887,7 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI26_0)
; RV64-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -911,7 +911,7 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI27_0)
; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -930,7 +930,7 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI27_0)
; RV64-NEXT: fld fa5, %lo(.LCPI27_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -1290,7 +1290,7 @@ define <vscale x 4 x i8> @rint_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI40_0)
; RV32-NEXT: fld fa5, %lo(.LCPI40_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1309,7 +1309,7 @@ define <vscale x 4 x i8> @rint_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI40_0)
; RV64-NEXT: fld fa5, %lo(.LCPI40_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1333,7 +1333,7 @@ define <vscale x 4 x i8> @rint_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI41_0)
; RV32-NEXT: fld fa5, %lo(.LCPI41_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1352,7 +1352,7 @@ define <vscale x 4 x i8> @rint_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI41_0)
; RV64-NEXT: fld fa5, %lo(.LCPI41_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1376,7 +1376,7 @@ define <vscale x 4 x i16> @rint_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI42_0)
; RV32-NEXT: fld fa5, %lo(.LCPI42_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1393,7 +1393,7 @@ define <vscale x 4 x i16> @rint_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI42_0)
; RV64-NEXT: fld fa5, %lo(.LCPI42_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1415,7 +1415,7 @@ define <vscale x 4 x i16> @rint_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI43_0)
; RV32-NEXT: fld fa5, %lo(.LCPI43_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vfabs.v v12, v8
+; RV32-NEXT: vfsgnjx.vv v12, v8, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1432,7 +1432,7 @@ define <vscale x 4 x i16> @rint_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI43_0)
; RV64-NEXT: fld fa5, %lo(.LCPI43_0)(a0)
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vfsgnjx.vv v12, v8, v8
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
index d8781495abd75c..1967f493127db1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
@@ -81,7 +81,7 @@ define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -104,7 +104,7 @@ define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -127,7 +127,7 @@ define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
@@ -194,7 +194,7 @@ define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -217,7 +217,7 @@ define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -240,7 +240,7 @@ define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -288,7 +288,7 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -311,7 +311,7 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
@@ -334,7 +334,7 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
index 9efc3183f15a52..f24a59bdfaf5f0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
@@ -70,7 +70,7 @@ define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -90,7 +90,7 @@ define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -110,7 +110,7 @@ define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -168,7 +168,7 @@ define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: ceil_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -188,7 +188,7 @@ define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: ceil_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -208,7 +208,7 @@ define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: ceil_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -250,7 +250,7 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -270,7 +270,7 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -290,7 +290,7 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
index 1df452d8641c58..f962f80a8df717 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
@@ -81,7 +81,7 @@ define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -104,7 +104,7 @@ define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -127,7 +127,7 @@ define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
@@ -194,7 +194,7 @@ define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -217,7 +217,7 @@ define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -240,7 +240,7 @@ define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -288,7 +288,7 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -311,7 +311,7 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
@@ -334,7 +334,7 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
index ec60b3ed3e0c88..6520ec57c88641 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
@@ -70,7 +70,7 @@ define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -90,7 +90,7 @@ define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -110,7 +110,7 @@ define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -168,7 +168,7 @@ define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: floor_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -188,7 +188,7 @@ define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: floor_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -208,7 +208,7 @@ define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: floor_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -250,7 +250,7 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -270,7 +270,7 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -290,7 +290,7 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
index befbfb88550bad..d89edc7bd848dc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
@@ -198,7 +198,7 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <8 x half> @vp_ceil_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 3
@@ -284,7 +284,7 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <16 x half> @vp_ceil_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <16 x half> @vp_ceil_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -433,7 +433,7 @@ define <8 x float> @vp_ceil_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -455,7 +455,7 @@ define <8 x float> @vp_ceil_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ceil_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -477,7 +477,7 @@ define <16 x float> @vp_ceil_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -499,7 +499,7 @@ define <16 x float> @vp_ceil_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl)
; CHECK-LABEL: vp_ceil_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -565,7 +565,7 @@ define <4 x double> @vp_ceil_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %e
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -587,7 +587,7 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -609,7 +609,7 @@ define <8 x double> @vp_ceil_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %e
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -631,7 +631,7 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -653,7 +653,7 @@ define <15 x double> @vp_ceil_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -675,7 +675,7 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -697,7 +697,7 @@ define <16 x double> @vp_ceil_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -719,7 +719,7 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -756,7 +756,7 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a1, 3
@@ -777,7 +777,7 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
@@ -809,7 +809,7 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -822,7 +822,7 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index f5e6b929051939..b41b0a853c19ec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -478,7 +478,7 @@ define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -515,7 +515,7 @@ define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v10
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -720,7 +720,7 @@ define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -760,7 +760,7 @@ define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 16
; CHECK-NEXT: vor.vv v8, v8, v10
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -802,7 +802,7 @@ define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -842,7 +842,7 @@ define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 16
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -1097,7 +1097,7 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -1149,7 +1149,7 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v10, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1201,7 +1201,7 @@ define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vor.vv v8, v8, v10
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -1253,7 +1253,7 @@ define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vor.vv v8, v8, v10
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v10, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1307,7 +1307,7 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -1359,7 +1359,7 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v12, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1411,7 +1411,7 @@ define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -1463,7 +1463,7 @@ define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vor.vv v8, v8, v12
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v12, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1539,7 +1539,7 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
+; RV32-NEXT: vxor.vi v24, v8, -1, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: addi a1, sp, 40
@@ -1611,7 +1611,7 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1681,7 +1681,7 @@ define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero
@@ -1726,7 +1726,7 @@ define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1802,7 +1802,7 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
+; RV32-NEXT: vxor.vi v24, v8, -1, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: addi a1, sp, 40
@@ -1874,7 +1874,7 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -1944,7 +1944,7 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero
@@ -1989,7 +1989,7 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -2079,7 +2079,7 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
@@ -2246,7 +2246,7 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
@@ -2377,7 +2377,7 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a2, a2, 1365
@@ -2432,7 +2432,7 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsub.vv v8, v8, v16, v0.t
@@ -2506,7 +2506,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a2, 32
; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vor.vv v8, v8, v24
-; RV32-NEXT: vnot.v v0, v8
+; RV32-NEXT: vxor.vi v0, v8, -1
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero
@@ -2546,7 +2546,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vsrl.vx v0, v24, a2
; RV32-NEXT: vor.vv v24, v24, v0
-; RV32-NEXT: vnot.v v24, v24
+; RV32-NEXT: vxor.vi v24, v24, -1
; RV32-NEXT: vsrl.vi v0, v24, 1
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: addi a2, sp, 24
@@ -2607,7 +2607,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: vor.vv v8, v8, v24
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v24, v8, 1
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a2, a2, 1365
@@ -2654,7 +2654,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: vsrl.vx v24, v16, a1
; RV64-NEXT: vor.vv v16, v16, v24
-; RV64-NEXT: vnot.v v16, v16
+; RV64-NEXT: vxor.vi v16, v16, -1
; RV64-NEXT: vsrl.vi v24, v16, 1
; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vsub.vv v16, v16, v24
@@ -3130,7 +3130,7 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -3167,7 +3167,7 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v10
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
@@ -3366,7 +3366,7 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -3406,7 +3406,7 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 16
; CHECK-NEXT: vor.vv v8, v8, v10
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -3446,7 +3446,7 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -3486,7 +3486,7 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 16
; CHECK-NEXT: vor.vv v8, v8, v12
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
@@ -3737,7 +3737,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -3789,7 +3789,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v10, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -3841,7 +3841,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vor.vv v8, v8, v10
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -3893,7 +3893,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vor.vv v8, v8, v10
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v10, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -3945,7 +3945,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -3997,7 +3997,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v12, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4049,7 +4049,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
@@ -4101,7 +4101,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vor.vv v8, v8, v12
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v12, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4175,7 +4175,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
+; RV32-NEXT: vxor.vi v24, v8, -1, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: addi a1, sp, 40
@@ -4247,7 +4247,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4317,7 +4317,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero
@@ -4362,7 +4362,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4436,7 +4436,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
+; RV32-NEXT: vxor.vi v24, v8, -1, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: addi a1, sp, 40
@@ -4508,7 +4508,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4578,7 +4578,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero
@@ -4623,7 +4623,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
; RV64-NEXT: addiw a0, a0, 1365
@@ -4711,7 +4711,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
@@ -4878,7 +4878,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
@@ -5009,7 +5009,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a2, a2, 1365
@@ -5064,7 +5064,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsub.vv v8, v8, v16, v0.t
@@ -5138,7 +5138,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV32-NEXT: li a2, 32
; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vor.vv v8, v8, v24
-; RV32-NEXT: vnot.v v0, v8
+; RV32-NEXT: vxor.vi v0, v8, -1
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero
@@ -5178,7 +5178,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vsrl.vx v0, v24, a2
; RV32-NEXT: vor.vv v24, v24, v0
-; RV32-NEXT: vnot.v v24, v24
+; RV32-NEXT: vxor.vi v24, v24, -1
; RV32-NEXT: vsrl.vi v0, v24, 1
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: addi a2, sp, 24
@@ -5239,7 +5239,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: vor.vv v8, v8, v24
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vsrl.vi v24, v8, 1
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a2, a2, 1365
@@ -5286,7 +5286,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: vsrl.vx v24, v16, a1
; RV64-NEXT: vor.vv v16, v16, v24
-; RV64-NEXT: vnot.v v16, v16
+; RV64-NEXT: vxor.vi v16, v16, -1
; RV64-NEXT: vsrl.vi v24, v16, 1
; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vsub.vv v16, v16, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 228a9f0d6d5221..afe9e857d7bc88 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -407,7 +407,7 @@ define void @ctlz_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 4
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: li a1, 85
; RVI-NEXT: vand.vx v10, v10, a1
@@ -486,7 +486,7 @@ define void @ctlz_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 8
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 5
; RVI-NEXT: addi a1, a1, 1365
@@ -565,7 +565,7 @@ define void @ctlz_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 16
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 349525
; RVI-NEXT: addi a1, a1, 1365
@@ -651,7 +651,7 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: li a1, 32
; RV32I-NEXT: vsrl.vx v10, v8, a1
; RV32I-NEXT: vor.vv v8, v8, v10
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
@@ -705,7 +705,7 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: vsrl.vx v10, v8, a1
; RV64I-NEXT: vor.vv v8, v8, v10
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365
@@ -1164,7 +1164,7 @@ define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 4
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: li a1, 85
; RVI-NEXT: vand.vx v10, v10, a1
@@ -1238,7 +1238,7 @@ define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 8
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 5
; RVI-NEXT: addi a1, a1, 1365
@@ -1312,7 +1312,7 @@ define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vor.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 16
; RVI-NEXT: vor.vv v8, v8, v10
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 349525
; RVI-NEXT: addi a1, a1, 1365
@@ -1393,7 +1393,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: li a1, 32
; RV32I-NEXT: vsrl.vx v10, v8, a1
; RV32I-NEXT: vor.vv v8, v8, v10
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
@@ -1447,7 +1447,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: vsrl.vx v10, v8, a1
; RV64I-NEXT: vor.vv v8, v8, v10
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index dfad7881066a27..87863d633ecf7d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -418,7 +418,7 @@ define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -450,7 +450,7 @@ define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -620,7 +620,7 @@ define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -653,7 +653,7 @@ define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -688,7 +688,7 @@ define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -721,7 +721,7 @@ define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -926,7 +926,7 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -968,7 +968,7 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v10, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1010,7 +1010,7 @@ define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -1052,7 +1052,7 @@ define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1096,7 +1096,7 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -1138,7 +1138,7 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v12, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1180,7 +1180,7 @@ define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -1222,7 +1222,7 @@ define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1288,7 +1288,7 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
@@ -1350,7 +1350,7 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1410,7 +1410,7 @@ define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1445,7 +1445,7 @@ define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1511,7 +1511,7 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
@@ -1573,7 +1573,7 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -1633,7 +1633,7 @@ define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1668,7 +1668,7 @@ define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -1748,7 +1748,7 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
@@ -1905,7 +1905,7 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vxor.vi v16, v16, -1, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
@@ -2026,7 +2026,7 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
@@ -2071,7 +2071,7 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vl8r.v v8, (a7) # Unknown-size Folded Reload
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
@@ -2135,7 +2135,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v24, v8, a2
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v0, v8, v24
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -2165,7 +2165,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-NEXT: vl8r.v v0, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v24, v0, a2
-; RV32-NEXT: vnot.v v0, v0
+; RV32-NEXT: vxor.vi v0, v0, -1
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v24, 1
; RV32-NEXT: vand.vv v16, v0, v16
@@ -2216,7 +2216,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a2, 1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v8, a2
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v24
; RV64-NEXT: vsrl.vi v24, v8, 1
; RV64-NEXT: lui a1, 349525
@@ -2253,7 +2253,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v16, a2
-; RV64-NEXT: vnot.v v16, v16
+; RV64-NEXT: vxor.vi v16, v16, -1
; RV64-NEXT: vand.vv v16, v16, v24
; RV64-NEXT: vsrl.vi v24, v16, 1
; RV64-NEXT: vand.vx v24, v24, a1
@@ -2670,7 +2670,7 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 5
@@ -2702,7 +2702,7 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 5
@@ -2866,7 +2866,7 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -2899,7 +2899,7 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -2932,7 +2932,7 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: lui a0, 349525
@@ -2965,7 +2965,7 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: lui a0, 349525
@@ -3166,7 +3166,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -3208,7 +3208,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v10, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -3250,7 +3250,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -3292,7 +3292,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsub.vx v10, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -3334,7 +3334,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
@@ -3376,7 +3376,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v12, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -3418,7 +3418,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: lui a1, 349525
@@ -3460,7 +3460,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsub.vx v12, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -3524,7 +3524,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
@@ -3586,7 +3586,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -3646,7 +3646,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -3681,7 +3681,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -3745,7 +3745,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
@@ -3807,7 +3807,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a0, 349525
@@ -3867,7 +3867,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -3902,7 +3902,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 1
; RV64-NEXT: lui a0, 349525
@@ -3980,7 +3980,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vxor.vi v8, v8, -1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
@@ -4137,7 +4137,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vxor.vi v16, v16, -1, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
@@ -4258,7 +4258,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
@@ -4303,7 +4303,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: vl8r.v v8, (a7) # Unknown-size Folded Reload
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vxor.vi v8, v8, -1, v0.t
; RV64-NEXT: vand.vv v8, v8, v16, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
@@ -4367,7 +4367,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v24, v8, a2
-; RV32-NEXT: vnot.v v8, v8
+; RV32-NEXT: vxor.vi v8, v8, -1
; RV32-NEXT: vand.vv v0, v8, v24
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -4397,7 +4397,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV32-NEXT: vl8r.v v0, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v24, v0, a2
-; RV32-NEXT: vnot.v v0, v0
+; RV32-NEXT: vxor.vi v0, v0, -1
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v24, 1
; RV32-NEXT: vand.vv v16, v0, v16
@@ -4448,7 +4448,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: li a2, 1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v8, a2
-; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vxor.vi v8, v8, -1
; RV64-NEXT: vand.vv v8, v8, v24
; RV64-NEXT: vsrl.vi v24, v8, 1
; RV64-NEXT: lui a1, 349525
@@ -4485,7 +4485,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsub.vx v24, v16, a2
-; RV64-NEXT: vnot.v v16, v16
+; RV64-NEXT: vxor.vi v16, v16, -1
; RV64-NEXT: vand.vv v16, v16, v24
; RV64-NEXT: vsrl.vi v24, v16, 1
; RV64-NEXT: vand.vx v24, v24, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index 4b1691aada5bef..f3b0c35fc8fc04 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -392,7 +392,7 @@ define void @cttz_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle8.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: li a1, 85
@@ -472,7 +472,7 @@ define void @cttz_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle16.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 5
@@ -550,7 +550,7 @@ define void @cttz_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle32.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 349525
@@ -632,7 +632,7 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vle64.v v8, (a0)
; RV32I-NEXT: li a1, 1
; RV32I-NEXT: vsub.vx v10, v8, a1
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v10
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a1, 349525
@@ -676,7 +676,7 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vle64.v v8, (a0)
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: vsub.vx v10, v8, a1
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v10
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a1, 349525
@@ -1121,7 +1121,7 @@ define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle8.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: li a1, 85
@@ -1196,7 +1196,7 @@ define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle16.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 5
@@ -1267,7 +1267,7 @@ define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vle32.v v8, (a0)
; RVI-NEXT: li a1, 1
; RVI-NEXT: vsub.vx v10, v8, a1
-; RVI-NEXT: vnot.v v8, v8
+; RVI-NEXT: vxor.vi v8, v8, -1
; RVI-NEXT: vand.vv v8, v8, v10
; RVI-NEXT: vsrl.vi v10, v8, 1
; RVI-NEXT: lui a1, 349525
@@ -1342,7 +1342,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vle64.v v8, (a0)
; RV32I-NEXT: li a1, 1
; RV32I-NEXT: vsub.vx v10, v8, a1
-; RV32I-NEXT: vnot.v v8, v8
+; RV32I-NEXT: vxor.vi v8, v8, -1
; RV32I-NEXT: vand.vv v8, v8, v10
; RV32I-NEXT: vsrl.vi v10, v8, 1
; RV32I-NEXT: lui a1, 349525
@@ -1386,7 +1386,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vle64.v v8, (a0)
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: vsub.vx v10, v8, a1
-; RV64I-NEXT: vnot.v v8, v8
+; RV64I-NEXT: vxor.vi v8, v8, -1
; RV64I-NEXT: vand.vv v8, v8, v10
; RV64I-NEXT: vsrl.vi v10, v8, 1
; RV64I-NEXT: lui a1, 349525
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
index 404fb72b8abe91..8a2e541543fbeb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
@@ -104,7 +104,7 @@ define <16 x half> @ceil_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -128,7 +128,7 @@ define <32 x half> @ceil_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -218,7 +218,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -241,7 +241,7 @@ define <16 x float> @ceil_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -312,7 +312,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -335,7 +335,7 @@ define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
index 2319aab370d2de..e6d0c7fbfb9c36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
@@ -104,7 +104,7 @@ define <16 x half> @floor_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -128,7 +128,7 @@ define <32 x half> @floor_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -218,7 +218,7 @@ define <8 x float> @floor_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -241,7 +241,7 @@ define <16 x float> @floor_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -312,7 +312,7 @@ define <4 x double> @floor_v4f64(<4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -335,7 +335,7 @@ define <8 x double> @floor_v8f64(<8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
index c1b4c5fda6c640..2ea4f85ccd526d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
@@ -198,7 +198,7 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <8 x half> @vp_floor_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 2
@@ -284,7 +284,7 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <16 x half> @vp_floor_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <16 x half> @vp_floor_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -433,7 +433,7 @@ define <8 x float> @vp_floor_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -455,7 +455,7 @@ define <8 x float> @vp_floor_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_floor_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -477,7 +477,7 @@ define <16 x float> @vp_floor_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -499,7 +499,7 @@ define <16 x float> @vp_floor_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-LABEL: vp_floor_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -565,7 +565,7 @@ define <4 x double> @vp_floor_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -587,7 +587,7 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -609,7 +609,7 @@ define <8 x double> @vp_floor_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -631,7 +631,7 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -653,7 +653,7 @@ define <15 x double> @vp_floor_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -675,7 +675,7 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -697,7 +697,7 @@ define <16 x double> @vp_floor_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -719,7 +719,7 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -756,7 +756,7 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a1, 2
@@ -777,7 +777,7 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -809,7 +809,7 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -822,7 +822,7 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
index 719dd524942846..abc8fc6dbd20b7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
@@ -86,7 +86,7 @@ define <16 x half> @nearbyint_v16f16(<16 x half> %v) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -111,7 +111,7 @@ define <32 x half> @nearbyint_v32f16(<32 x half> %v) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -181,7 +181,7 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %v) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -205,7 +205,7 @@ define <16 x float> @nearbyint_v16f32(<16 x float> %v) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -255,7 +255,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %v) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -279,7 +279,7 @@ define <8 x double> @nearbyint_v8f64(<8 x double> %v) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index d25312268ada62..fe0e6f0da6e215 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -2048,7 +2048,7 @@ define void @fneg_v16f16(ptr %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT: vle16.v v8, (a0)
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
;
@@ -2058,7 +2058,7 @@ define void @fneg_v16f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v8, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
@@ -2074,7 +2074,7 @@ define void @fneg_v8f32(ptr %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFH-NEXT: vle32.v v8, (a0)
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: vse32.v v8, (a0)
; ZVFH-NEXT: ret
;
@@ -2096,7 +2096,7 @@ define void @fneg_v4f64(ptr %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVFH-NEXT: vle64.v v8, (a0)
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: vse64.v v8, (a0)
; ZVFH-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
index e855d9504ff404..ec7429e5d84806 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
@@ -106,7 +106,7 @@ define <16 x half> @round_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -130,7 +130,7 @@ define <32 x half> @round_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -220,7 +220,7 @@ define <8 x float> @round_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -243,7 +243,7 @@ define <16 x float> @round_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -314,7 +314,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -337,7 +337,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
index 3f1bc03435840b..3ac8cd7e7f3e2e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
@@ -148,7 +148,7 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -172,7 +172,7 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFH-NEXT: lui a0, %hi(.LCPI4_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -187,7 +187,7 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -212,7 +212,7 @@ define <32 x half> @round_v32f16(<32 x half> %x) {
; ZVFH-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; ZVFH-NEXT: li a0, 32
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -228,7 +228,7 @@ define <32 x half> @round_v32f16(<32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -310,7 +310,7 @@ define <8 x float> @round_v8f32(<8 x float> %x) {
; CHECK-LABEL: round_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -330,7 +330,7 @@ define <16 x float> @round_v16f32(<16 x float> %x) {
; CHECK-LABEL: round_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -392,7 +392,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -412,7 +412,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
index 9976cd2a8ab29a..8c6c71d9c244be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
@@ -106,7 +106,7 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -130,7 +130,7 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -220,7 +220,7 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -243,7 +243,7 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -314,7 +314,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -337,7 +337,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
index 9607aa09d89d68..71900eebc54d0a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
@@ -148,7 +148,7 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -172,7 +172,7 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFH-NEXT: lui a0, %hi(.LCPI4_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -187,7 +187,7 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -212,7 +212,7 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) {
; ZVFH-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; ZVFH-NEXT: li a0, 32
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -228,7 +228,7 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -310,7 +310,7 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) {
; CHECK-LABEL: roundeven_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -330,7 +330,7 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) {
; CHECK-LABEL: roundeven_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -392,7 +392,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -412,7 +412,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
index a2ff77625b7584..8c4187f12cb500 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
@@ -144,7 +144,7 @@ define <32 x i8> @fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
@@ -161,7 +161,7 @@ define <32 x i8> @fshl_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
@@ -178,7 +178,7 @@ define <64 x i8> @fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
@@ -195,7 +195,7 @@ define <64 x i8> @fshl_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
@@ -314,7 +314,7 @@ define <16 x i16> @fshr_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
@@ -331,7 +331,7 @@ define <16 x i16> @fshl_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
@@ -348,7 +348,7 @@ define <32 x i16> @fshr_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
@@ -365,7 +365,7 @@ define <32 x i16> @fshl_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
@@ -456,7 +456,7 @@ define <8 x i32> @fshr_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
@@ -474,7 +474,7 @@ define <8 x i32> @fshl_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
@@ -492,7 +492,7 @@ define <16 x i32> @fshr_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
@@ -510,7 +510,7 @@ define <16 x i32> @fshl_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
@@ -564,7 +564,7 @@ define <4 x i64> @fshr_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
@@ -582,7 +582,7 @@ define <4 x i64> @fshl_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
@@ -600,7 +600,7 @@ define <7 x i64> @fshr_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
@@ -618,7 +618,7 @@ define <7 x i64> @fshl_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
@@ -636,7 +636,7 @@ define <8 x i64> @fshr_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
@@ -654,7 +654,7 @@ define <8 x i64> @fshl_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
@@ -682,7 +682,7 @@ define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -717,7 +717,7 @@ define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: vxor.vi v16, v24, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
index eac26451d5a8cc..7766b58daf7c90 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
@@ -96,7 +96,7 @@ define <16 x half> @trunc_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -118,7 +118,7 @@ define <32 x half> @trunc_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -200,7 +200,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -221,7 +221,7 @@ define <16 x float> @trunc_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -286,7 +286,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -307,7 +307,7 @@ define <8 x double> @trunc_v8f64(<8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
index 93b4f7d2a9c9fd..ea733f9d4ca6ba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
@@ -139,7 +139,7 @@ define <16 x half> @vp_nearbyint_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe
; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -161,7 +161,7 @@ define <16 x half> @vp_nearbyint_v16f16_unmasked(<16 x half> %va, i32 zeroext %e
; CHECK-NEXT: lui a1, %hi(.LCPI7_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -265,7 +265,7 @@ define <8 x float> @vp_nearbyint_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -287,7 +287,7 @@ define <8 x float> @vp_nearbyint_v8f32_unmasked(<8 x float> %va, i32 zeroext %ev
; CHECK-LABEL: vp_nearbyint_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -309,7 +309,7 @@ define <16 x float> @vp_nearbyint_v16f32(<16 x float> %va, <16 x i1> %m, i32 zer
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -331,7 +331,7 @@ define <16 x float> @vp_nearbyint_v16f32_unmasked(<16 x float> %va, i32 zeroext
; CHECK-LABEL: vp_nearbyint_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -397,7 +397,7 @@ define <4 x double> @vp_nearbyint_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -419,7 +419,7 @@ define <4 x double> @vp_nearbyint_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -441,7 +441,7 @@ define <8 x double> @vp_nearbyint_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -463,7 +463,7 @@ define <8 x double> @vp_nearbyint_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -485,7 +485,7 @@ define <15 x double> @vp_nearbyint_v15f64(<15 x double> %va, <15 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -507,7 +507,7 @@ define <15 x double> @vp_nearbyint_v15f64_unmasked(<15 x double> %va, i32 zeroex
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -529,7 +529,7 @@ define <16 x double> @vp_nearbyint_v16f64(<16 x double> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -551,7 +551,7 @@ define <16 x double> @vp_nearbyint_v16f64_unmasked(<16 x double> %va, i32 zeroex
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -582,7 +582,7 @@ define <32 x double> @vp_nearbyint_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: frflags a1
@@ -599,7 +599,7 @@ define <32 x double> @vp_nearbyint_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -627,7 +627,7 @@ define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroex
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -640,7 +640,7 @@ define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroex
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
index 1f856d04ca89fd..9a3127017de143 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
@@ -127,7 +127,7 @@ define <16 x half> @vp_rint_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e
; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
@@ -147,7 +147,7 @@ define <16 x half> @vp_rint_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {
; CHECK-NEXT: lui a1, %hi(.LCPI7_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -241,7 +241,7 @@ define <8 x float> @vp_rint_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -261,7 +261,7 @@ define <8 x float> @vp_rint_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_rint_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -281,7 +281,7 @@ define <16 x float> @vp_rint_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -301,7 +301,7 @@ define <16 x float> @vp_rint_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl)
; CHECK-LABEL: vp_rint_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -361,7 +361,7 @@ define <4 x double> @vp_rint_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %e
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
@@ -381,7 +381,7 @@ define <4 x double> @vp_rint_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -401,7 +401,7 @@ define <8 x double> @vp_rint_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %e
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
@@ -421,7 +421,7 @@ define <8 x double> @vp_rint_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -441,7 +441,7 @@ define <15 x double> @vp_rint_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
@@ -461,7 +461,7 @@ define <15 x double> @vp_rint_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -481,7 +481,7 @@ define <16 x double> @vp_rint_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
@@ -501,7 +501,7 @@ define <16 x double> @vp_rint_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -536,7 +536,7 @@ define <32 x double> @vp_rint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
@@ -554,7 +554,7 @@ define <32 x double> @vp_rint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v7
@@ -584,14 +584,14 @@ define <32 x double> @vp_rint_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: addi a2, a0, -16
; CHECK-NEXT: sltu a0, a0, a2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v7, v24, fa5
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
index 0f587232680df6..01aeb5dda8a55a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
@@ -198,7 +198,7 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <8 x half> @vp_round_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 4
@@ -284,7 +284,7 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <16 x half> @vp_round_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <16 x half> @vp_round_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -433,7 +433,7 @@ define <8 x float> @vp_round_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -455,7 +455,7 @@ define <8 x float> @vp_round_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_round_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -477,7 +477,7 @@ define <16 x float> @vp_round_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -499,7 +499,7 @@ define <16 x float> @vp_round_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-LABEL: vp_round_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -565,7 +565,7 @@ define <4 x double> @vp_round_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -587,7 +587,7 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -609,7 +609,7 @@ define <8 x double> @vp_round_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -631,7 +631,7 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -653,7 +653,7 @@ define <15 x double> @vp_round_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -675,7 +675,7 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -697,7 +697,7 @@ define <16 x double> @vp_round_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -719,7 +719,7 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -756,7 +756,7 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a1, 4
@@ -777,7 +777,7 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -809,7 +809,7 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -822,7 +822,7 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
index 0fb7e6a7de5696..35ae0b2256c553 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
@@ -198,7 +198,7 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <8 x half> @vp_roundeven_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 0
@@ -284,7 +284,7 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %e
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %e
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -433,7 +433,7 @@ define <8 x float> @vp_roundeven_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -455,7 +455,7 @@ define <8 x float> @vp_roundeven_v8f32_unmasked(<8 x float> %va, i32 zeroext %ev
; CHECK-LABEL: vp_roundeven_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -477,7 +477,7 @@ define <16 x float> @vp_roundeven_v16f32(<16 x float> %va, <16 x i1> %m, i32 zer
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -499,7 +499,7 @@ define <16 x float> @vp_roundeven_v16f32_unmasked(<16 x float> %va, i32 zeroext
; CHECK-LABEL: vp_roundeven_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -565,7 +565,7 @@ define <4 x double> @vp_roundeven_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -587,7 +587,7 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -609,7 +609,7 @@ define <8 x double> @vp_roundeven_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -631,7 +631,7 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -653,7 +653,7 @@ define <15 x double> @vp_roundeven_v15f64(<15 x double> %va, <15 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -675,7 +675,7 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -697,7 +697,7 @@ define <16 x double> @vp_roundeven_v16f64(<16 x double> %va, <16 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -719,7 +719,7 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -756,7 +756,7 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a1, 0
@@ -777,7 +777,7 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -809,7 +809,7 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -822,7 +822,7 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
index 927f96b6442274..35e65382a7c1a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
@@ -198,7 +198,7 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <8 x half> @vp_roundtozero_v8f16_unmasked(<8 x half> %va, i32 zeroext %ev
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 1
@@ -284,7 +284,7 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <16 x half> @vp_roundtozero_v16f16_unmasked(<16 x half> %va, i32 zeroext
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <16 x half> @vp_roundtozero_v16f16_unmasked(<16 x half> %va, i32 zeroext
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -433,7 +433,7 @@ define <8 x float> @vp_roundtozero_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -455,7 +455,7 @@ define <8 x float> @vp_roundtozero_v8f32_unmasked(<8 x float> %va, i32 zeroext %
; CHECK-LABEL: vp_roundtozero_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -477,7 +477,7 @@ define <16 x float> @vp_roundtozero_v16f32(<16 x float> %va, <16 x i1> %m, i32 z
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -499,7 +499,7 @@ define <16 x float> @vp_roundtozero_v16f32_unmasked(<16 x float> %va, i32 zeroex
; CHECK-LABEL: vp_roundtozero_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -565,7 +565,7 @@ define <4 x double> @vp_roundtozero_v4f64(<4 x double> %va, <4 x i1> %m, i32 zer
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -587,7 +587,7 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext
; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -609,7 +609,7 @@ define <8 x double> @vp_roundtozero_v8f64(<8 x double> %va, <8 x i1> %m, i32 zer
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -631,7 +631,7 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext
; CHECK-NEXT: lui a1, %hi(.LCPI21_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -653,7 +653,7 @@ define <15 x double> @vp_roundtozero_v15f64(<15 x double> %va, <15 x i1> %m, i32
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -675,7 +675,7 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero
; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -697,7 +697,7 @@ define <16 x double> @vp_roundtozero_v16f64(<16 x double> %va, <16 x i1> %m, i32
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -719,7 +719,7 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -756,7 +756,7 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a1, 1
@@ -777,7 +777,7 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -809,7 +809,7 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a1, 1
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
@@ -822,7 +822,7 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
index ae3dce497c6d07..d34c12afa3460e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
@@ -106,7 +106,7 @@ define <8 x half> @vfabs_vv_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v10, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v10, v10, v10, v0.t
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -126,7 +126,7 @@ define <8 x half> @vfabs_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -140,7 +140,7 @@ define <16 x half> @vfabs_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFH-LABEL: vfabs_vv_v16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_v16f16:
@@ -148,7 +148,7 @@ define <16 x half> @vfabs_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v12, v12, v0.t
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -160,7 +160,7 @@ define <16 x half> @vfabs_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-LABEL: vfabs_vv_v16f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_v16f16_unmasked:
@@ -168,7 +168,7 @@ define <16 x half> @vfabs_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -226,7 +226,7 @@ define <8 x float> @vfabs_vv_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vfabs_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -236,7 +236,7 @@ define <8 x float> @vfabs_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)
ret <8 x float> %v
@@ -248,7 +248,7 @@ define <16 x float> @vfabs_vv_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK-LABEL: vfabs_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)
ret <16 x float> %v
@@ -258,7 +258,7 @@ define <16 x float> @vfabs_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-LABEL: vfabs_vv_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x float> %v
@@ -292,7 +292,7 @@ define <4 x double> @vfabs_vv_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %
; CHECK-LABEL: vfabs_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
@@ -302,7 +302,7 @@ define <4 x double> @vfabs_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-LABEL: vfabs_vv_v4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x double> %v
@@ -314,7 +314,7 @@ define <8 x double> @vfabs_vv_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %
; CHECK-LABEL: vfabs_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)
ret <8 x double> %v
@@ -324,7 +324,7 @@ define <8 x double> @vfabs_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-LABEL: vfabs_vv_v8f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)
ret <8 x double> %v
@@ -336,7 +336,7 @@ define <15 x double> @vfabs_vv_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe
; CHECK-LABEL: vfabs_vv_v15f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)
ret <15 x double> %v
@@ -346,7 +346,7 @@ define <15 x double> @vfabs_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; CHECK-LABEL: vfabs_vv_v15f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)
ret <15 x double> %v
@@ -358,7 +358,7 @@ define <16 x double> @vfabs_vv_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe
; CHECK-LABEL: vfabs_vv_v16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)
ret <16 x double> %v
@@ -368,7 +368,7 @@ define <16 x double> @vfabs_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; CHECK-LABEL: vfabs_vv_v16f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x double> %v
@@ -388,14 +388,14 @@ define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v16, v16, v0.t
; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v
@@ -411,13 +411,13 @@ define <32 x double> @vfabs_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v16
+; CHECK-NEXT: vfsgnjx.vv v16, v16, v16
; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)
ret <32 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
index fbc4c56a911340..f38661d5501b5b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
@@ -106,7 +106,7 @@ define <8 x half> @vfneg_vv_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10, v0.t
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -126,7 +126,7 @@ define <8 x half> @vfneg_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -140,7 +140,7 @@ define <16 x half> @vfneg_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFH-LABEL: vfneg_vv_v16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_v16f16:
@@ -148,7 +148,7 @@ define <16 x half> @vfneg_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12, v0.t
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -160,7 +160,7 @@ define <16 x half> @vfneg_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-LABEL: vfneg_vv_v16f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_v16f16_unmasked:
@@ -168,7 +168,7 @@ define <16 x half> @vfneg_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -226,7 +226,7 @@ define <8 x float> @vfneg_vv_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vfneg_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -236,7 +236,7 @@ define <8 x float> @vfneg_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfneg_vv_v8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)
ret <8 x float> %v
@@ -248,7 +248,7 @@ define <16 x float> @vfneg_vv_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext
; CHECK-LABEL: vfneg_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)
ret <16 x float> %v
@@ -258,7 +258,7 @@ define <16 x float> @vfneg_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-LABEL: vfneg_vv_v16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x float> %v
@@ -292,7 +292,7 @@ define <4 x double> @vfneg_vv_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %
; CHECK-LABEL: vfneg_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
@@ -302,7 +302,7 @@ define <4 x double> @vfneg_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; CHECK-LABEL: vfneg_vv_v4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x double> %v
@@ -314,7 +314,7 @@ define <8 x double> @vfneg_vv_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %
; CHECK-LABEL: vfneg_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)
ret <8 x double> %v
@@ -324,7 +324,7 @@ define <8 x double> @vfneg_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; CHECK-LABEL: vfneg_vv_v8f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)
ret <8 x double> %v
@@ -336,7 +336,7 @@ define <15 x double> @vfneg_vv_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe
; CHECK-LABEL: vfneg_vv_v15f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)
ret <15 x double> %v
@@ -346,7 +346,7 @@ define <15 x double> @vfneg_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; CHECK-LABEL: vfneg_vv_v15f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)
ret <15 x double> %v
@@ -358,7 +358,7 @@ define <16 x double> @vfneg_vv_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe
; CHECK-LABEL: vfneg_vv_v16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)
ret <16 x double> %v
@@ -368,7 +368,7 @@ define <16 x double> @vfneg_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; CHECK-LABEL: vfneg_vv_v16f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x double> %v
@@ -388,14 +388,14 @@ define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v16, v16, v0.t
+; CHECK-NEXT: vfsgnjn.vv v16, v16, v16, v0.t
; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v
@@ -411,13 +411,13 @@ define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v16, v16
+; CHECK-NEXT: vfsgnjn.vv v16, v16, v16
; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)
ret <32 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
index 16487a0784125e..23607cda564ab3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
@@ -786,7 +786,7 @@ define <16 x i16> @vxor_vi_v16i16_1(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vxor_vi_v16i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -796,7 +796,7 @@ define <16 x i16> @vxor_vi_v16i16_unmasked_1(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v16i16_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i16> %v
@@ -1044,7 +1044,7 @@ define <8 x i32> @vxor_vi_v8i32_1(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vxor_vi_v8i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -1054,7 +1054,7 @@ define <8 x i32> @vxor_vi_v8i32_unmasked_1(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v8i32_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i32> %v
@@ -1130,7 +1130,7 @@ define <16 x i32> @vxor_vi_v16i32_1(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vxor_vi_v16i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -1140,7 +1140,7 @@ define <16 x i32> @vxor_vi_v16i32_unmasked_1(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v16i32_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i32> %v
@@ -1358,7 +1358,7 @@ define <4 x i64> @vxor_vi_v4i64_1(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vxor_vi_v4i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1368,7 +1368,7 @@ define <4 x i64> @vxor_vi_v4i64_unmasked_1(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v4i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i64> %v
@@ -1472,7 +1472,7 @@ define <8 x i64> @vxor_vi_v8i64_1(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vxor_vi_v8i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1482,7 +1482,7 @@ define <8 x i64> @vxor_vi_v8i64_unmasked_1(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v8i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i64> %v
@@ -1586,7 +1586,7 @@ define <16 x i64> @vxor_vi_v16i64_1(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vxor_vi_v16i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1596,7 +1596,7 @@ define <16 x i64> @vxor_vi_v16i64_unmasked_1(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vi_v16i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
index b7661bd826fed2..416aab370905b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
@@ -208,7 +208,7 @@ define <vscale x 4 x i8> @trunc_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV32-LABEL: trunc_nxv4f32_to_si8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -225,7 +225,7 @@ define <vscale x 4 x i8> @trunc_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV64-LABEL: trunc_nxv4f32_to_si8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
@@ -247,7 +247,7 @@ define <vscale x 4 x i8> @trunc_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV32-LABEL: trunc_nxv4f32_to_ui8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -264,7 +264,7 @@ define <vscale x 4 x i8> @trunc_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV64-LABEL: trunc_nxv4f32_to_ui8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
@@ -628,7 +628,7 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_si8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -647,7 +647,7 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV64-LABEL: ceil_nxv4f32_to_si8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
@@ -671,7 +671,7 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_ui8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -690,7 +690,7 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV64-LABEL: ceil_nxv4f32_to_ui8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
@@ -854,7 +854,7 @@ define <vscale x 4 x i8> @rint_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV32-LABEL: rint_nxv4f32_to_si8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -871,7 +871,7 @@ define <vscale x 4 x i8> @rint_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV64-LABEL: rint_nxv4f32_to_si8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
@@ -893,7 +893,7 @@ define <vscale x 4 x i8> @rint_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV32-LABEL: rint_nxv4f32_to_ui8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vfabs.v v10, v8
+; RV32-NEXT: vfsgnjx.vv v10, v8, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -910,7 +910,7 @@ define <vscale x 4 x i8> @rint_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV64-LABEL: rint_nxv4f32_to_ui8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vfsgnjx.vv v10, v8, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
index 26a3e053bf7aad..c7f0651887c016 100644
--- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
@@ -139,7 +139,7 @@ define <vscale x 8 x half> @vp_floor_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -161,7 +161,7 @@ define <vscale x 8 x half> @vp_floor_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; CHECK-NEXT: lui a1, %hi(.LCPI7_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -183,7 +183,7 @@ define <vscale x 16 x half> @vp_floor_nxv16f16(<vscale x 16 x half> %va, <vscale
; CHECK-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -205,7 +205,7 @@ define <vscale x 16 x half> @vp_floor_nxv16f16_unmasked(<vscale x 16 x half> %va
; CHECK-NEXT: lui a1, %hi(.LCPI9_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -227,7 +227,7 @@ define <vscale x 32 x half> @vp_floor_nxv32f16(<vscale x 32 x half> %va, <vscale
; CHECK-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -249,7 +249,7 @@ define <vscale x 32 x half> @vp_floor_nxv32f16_unmasked(<vscale x 32 x half> %va
; CHECK-NEXT: lui a1, %hi(.LCPI11_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -353,7 +353,7 @@ define <vscale x 4 x float> @vp_floor_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -375,7 +375,7 @@ define <vscale x 4 x float> @vp_floor_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vp_floor_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -397,7 +397,7 @@ define <vscale x 8 x float> @vp_floor_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -419,7 +419,7 @@ define <vscale x 8 x float> @vp_floor_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vp_floor_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -441,7 +441,7 @@ define <vscale x 16 x float> @vp_floor_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -463,7 +463,7 @@ define <vscale x 16 x float> @vp_floor_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-LABEL: vp_floor_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -529,7 +529,7 @@ define <vscale x 2 x double> @vp_floor_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -551,7 +551,7 @@ define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -573,7 +573,7 @@ define <vscale x 4 x double> @vp_floor_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -595,7 +595,7 @@ define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -617,7 +617,7 @@ define <vscale x 7 x double> @vp_floor_nxv7f64(<vscale x 7 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -639,7 +639,7 @@ define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -661,7 +661,7 @@ define <vscale x 8 x double> @vp_floor_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -683,7 +683,7 @@ define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -721,7 +721,7 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a2, 2
@@ -742,7 +742,7 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
@@ -773,7 +773,7 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a2, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -786,7 +786,7 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
index 372937bb5ca5df..0bdb920e7d6cfe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
@@ -86,7 +86,7 @@ define <vscale x 8 x half> @nearbyint_nxv8f16(<vscale x 8 x half> %v) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -110,7 +110,7 @@ define <vscale x 16 x half> @nearbyint_nxv16f16(<vscale x 16 x half> %v) strictf
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -134,7 +134,7 @@ define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %v) strictf
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
@@ -204,7 +204,7 @@ define <vscale x 4 x float> @nearbyint_nxv4f32(<vscale x 4 x float> %v) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -228,7 +228,7 @@ define <vscale x 8 x float> @nearbyint_nxv8f32(<vscale x 8 x float> %v) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -252,7 +252,7 @@ define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %v) stric
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -302,7 +302,7 @@ define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) strict
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -326,7 +326,7 @@ define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) strict
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
@@ -350,7 +350,7 @@ define <vscale x 8 x double> @nearbyint_nxv8f64(<vscale x 8 x double> %v) strict
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
index 9e14852305caa1..745b658fc684b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
@@ -70,7 +70,7 @@ define <vscale x 8 x half> @nearbyint_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -90,7 +90,7 @@ define <vscale x 16 x half> @nearbyint_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -110,7 +110,7 @@ define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -168,7 +168,7 @@ define <vscale x 4 x float> @nearbyint_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: nearbyint_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -188,7 +188,7 @@ define <vscale x 8 x float> @nearbyint_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: nearbyint_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -208,7 +208,7 @@ define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: nearbyint_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -250,7 +250,7 @@ define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -270,7 +270,7 @@ define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -290,7 +290,7 @@ define <vscale x 8 x double> @nearbyint_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
index fb77b746549400..669d572ad4fcf1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
@@ -64,7 +64,7 @@ define <vscale x 8 x half> @rint_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -82,7 +82,7 @@ define <vscale x 16 x half> @rint_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -100,7 +100,7 @@ define <vscale x 32 x half> @rint_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -152,7 +152,7 @@ define <vscale x 4 x float> @rint_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: rint_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -170,7 +170,7 @@ define <vscale x 8 x float> @rint_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: rint_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -188,7 +188,7 @@ define <vscale x 16 x float> @rint_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: rint_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -226,7 +226,7 @@ define <vscale x 2 x double> @rint_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -244,7 +244,7 @@ define <vscale x 4 x double> @rint_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -262,7 +262,7 @@ define <vscale x 8 x double> @rint_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
index aaa7a538e70fb7..03ca7d89f20379 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
@@ -83,7 +83,7 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -106,7 +106,7 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -129,7 +129,7 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
@@ -196,7 +196,7 @@ define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -219,7 +219,7 @@ define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -242,7 +242,7 @@ define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -290,7 +290,7 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -313,7 +313,7 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
@@ -336,7 +336,7 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
index bb6724eeb32006..4105a7a43fbd2d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
@@ -72,7 +72,7 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -92,7 +92,7 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -112,7 +112,7 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -170,7 +170,7 @@ define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: round_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -190,7 +190,7 @@ define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: round_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -210,7 +210,7 @@ define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: round_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -252,7 +252,7 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -272,7 +272,7 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -292,7 +292,7 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
index cdc01d658778bc..d6f0148884a160 100644
--- a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
@@ -83,7 +83,7 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -106,7 +106,7 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) strictf
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -129,7 +129,7 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) strictf
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
@@ -196,7 +196,7 @@ define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -219,7 +219,7 @@ define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -242,7 +242,7 @@ define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) stric
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -290,7 +290,7 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) strict
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -313,7 +313,7 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) strict
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
@@ -336,7 +336,7 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) strict
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
index 6f5207a25518f5..4c70b3eccc24ff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
@@ -72,7 +72,7 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -92,7 +92,7 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -112,7 +112,7 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -170,7 +170,7 @@ define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: roundeven_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -190,7 +190,7 @@ define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: roundeven_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -210,7 +210,7 @@ define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: roundeven_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -252,7 +252,7 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -272,7 +272,7 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -292,7 +292,7 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
index 2c5a3dfffc2cfc..96c9bf08a4b856 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
@@ -144,7 +144,7 @@ define <vscale x 16 x i8> @fshr_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
@@ -161,7 +161,7 @@ define <vscale x 16 x i8> @fshl_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
@@ -178,7 +178,7 @@ define <vscale x 32 x i8> @fshr_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
@@ -195,7 +195,7 @@ define <vscale x 32 x i8> @fshl_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
@@ -221,7 +221,7 @@ define <vscale x 64 x i8> @fshr_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8>
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vi v8, v8, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
; CHECK-NEXT: vand.vi v16, v24, 7, v0.t
@@ -252,7 +252,7 @@ define <vscale x 64 x i8> @fshl_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8>
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vi v8, v8, 7, v0.t
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: vand.vi v16, v24, 7, v0.t
@@ -376,7 +376,7 @@ define <vscale x 8 x i16> @fshr_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
@@ -393,7 +393,7 @@ define <vscale x 8 x i16> @fshl_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vxor.vi v14, v12, -1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
@@ -410,7 +410,7 @@ define <vscale x 16 x i16> @fshr_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
@@ -427,7 +427,7 @@ define <vscale x 16 x i16> @fshl_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vxor.vi v20, v16, -1, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
@@ -453,7 +453,7 @@ define <vscale x 32 x i16> @fshr_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
; CHECK-NEXT: vand.vi v16, v24, 15, v0.t
@@ -484,7 +484,7 @@ define <vscale x 32 x i16> @fshl_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: vand.vi v16, v24, 15, v0.t
@@ -580,7 +580,7 @@ define <vscale x 4 x i32> @fshr_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32>
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
@@ -598,7 +598,7 @@ define <vscale x 4 x i32> @fshl_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32>
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
@@ -616,7 +616,7 @@ define <vscale x 8 x i32> @fshr_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32>
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
@@ -634,7 +634,7 @@ define <vscale x 8 x i32> @fshl_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32>
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
@@ -661,7 +661,7 @@ define <vscale x 16 x i32> @fshr_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -695,7 +695,7 @@ define <vscale x 16 x i32> @fshl_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: vxor.vi v16, v24, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -755,7 +755,7 @@ define <vscale x 2 x i64> @fshr_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64>
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
@@ -773,7 +773,7 @@ define <vscale x 2 x i64> @fshl_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64>
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
+; CHECK-NEXT: vxor.vi v12, v12, -1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
@@ -791,7 +791,7 @@ define <vscale x 4 x i64> @fshr_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
@@ -809,7 +809,7 @@ define <vscale x 4 x i64> @fshl_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64>
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
+; CHECK-NEXT: vxor.vi v16, v16, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
@@ -836,7 +836,7 @@ define <vscale x 7 x i64> @fshr_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64>
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -870,7 +870,7 @@ define <vscale x 7 x i64> @fshl_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64>
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: vxor.vi v16, v24, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -903,7 +903,7 @@ define <vscale x 8 x i64> @fshr_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64>
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vxor.vi v8, v24, -1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -937,7 +937,7 @@ define <vscale x 8 x i64> @fshl_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64>
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: vxor.vi v16, v24, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
@@ -1020,7 +1020,7 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vl8r.v v8, (a5) # Unknown-size Folded Reload
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
@@ -1089,7 +1089,7 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vnot.v v16, v8, v0.t
+; CHECK-NEXT: vxor.vi v16, v8, -1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
@@ -1179,7 +1179,7 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
; CHECK-NEXT: vl8r.v v8, (a6) # Unknown-size Folded Reload
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vl8re64.v v16, (a5)
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: addi a5, sp, 16
@@ -1245,7 +1245,7 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vx v16, v8, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
index 21615b516da898..eeadbf9faa2cc3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
@@ -75,7 +75,7 @@ define <vscale x 8 x half> @trunc_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -96,7 +96,7 @@ define <vscale x 16 x half> @trunc_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -117,7 +117,7 @@ define <vscale x 32 x half> @trunc_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t
@@ -178,7 +178,7 @@ define <vscale x 4 x float> @trunc_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -199,7 +199,7 @@ define <vscale x 8 x float> @trunc_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -220,7 +220,7 @@ define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -264,7 +264,7 @@ define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -285,7 +285,7 @@ define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -306,7 +306,7 @@ define <vscale x 8 x double> @trunc_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
index 8841232e7f76df..9a48a6dfe67510 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
@@ -64,7 +64,7 @@ define <vscale x 8 x half> @trunc_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -82,7 +82,7 @@ define <vscale x 16 x half> @trunc_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -100,7 +100,7 @@ define <vscale x 32 x half> @trunc_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -152,7 +152,7 @@ define <vscale x 4 x float> @trunc_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: trunc_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -170,7 +170,7 @@ define <vscale x 8 x float> @trunc_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: trunc_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -188,7 +188,7 @@ define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: trunc_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -226,7 +226,7 @@ define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -244,7 +244,7 @@ define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -262,7 +262,7 @@ define <vscale x 8 x double> @trunc_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
index a3ea462b6a7376..fc8e2e7e5befdd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
@@ -198,7 +198,7 @@ define <vscale x 4 x half> @vp_nearbyint_nxv4f16(<vscale x 4 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <vscale x 4 x half> @vp_nearbyint_nxv4f16_unmasked(<vscale x 4 x half> %v
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <vscale x 8 x half> @vp_nearbyint_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: frflags a0
@@ -284,7 +284,7 @@ define <vscale x 8 x half> @vp_nearbyint_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <vscale x 8 x half> @vp_nearbyint_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: frflags a0
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <vscale x 8 x half> @vp_nearbyint_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -351,7 +351,7 @@ define <vscale x 16 x half> @vp_nearbyint_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; ZVFH-NEXT: vmv1r.v v12, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
; ZVFH-NEXT: frflags a0
@@ -370,7 +370,7 @@ define <vscale x 16 x half> @vp_nearbyint_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -396,7 +396,7 @@ define <vscale x 16 x half> @vp_nearbyint_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFH-NEXT: lui a1, %hi(.LCPI9_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: frflags a0
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -411,7 +411,7 @@ define <vscale x 16 x half> @vp_nearbyint_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -437,7 +437,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; ZVFH-NEXT: vmv1r.v v16, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v24, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
; ZVFH-NEXT: frflags a0
@@ -474,7 +474,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -498,7 +498,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v7, v16, fa5, v0.t
; ZVFHMIN-NEXT: frflags a0
@@ -526,7 +526,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFH-NEXT: lui a1, %hi(.LCPI11_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: frflags a0
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -561,7 +561,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -584,7 +584,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT: frflags a0
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -694,7 +694,7 @@ define <vscale x 4 x float> @vp_nearbyint_nxv4f32(<vscale x 4 x float> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -716,7 +716,7 @@ define <vscale x 4 x float> @vp_nearbyint_nxv4f32_unmasked(<vscale x 4 x float>
; CHECK-LABEL: vp_nearbyint_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -738,7 +738,7 @@ define <vscale x 8 x float> @vp_nearbyint_nxv8f32(<vscale x 8 x float> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -760,7 +760,7 @@ define <vscale x 8 x float> @vp_nearbyint_nxv8f32_unmasked(<vscale x 8 x float>
; CHECK-LABEL: vp_nearbyint_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -782,7 +782,7 @@ define <vscale x 16 x float> @vp_nearbyint_nxv16f32(<vscale x 16 x float> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -804,7 +804,7 @@ define <vscale x 16 x float> @vp_nearbyint_nxv16f32_unmasked(<vscale x 16 x floa
; CHECK-LABEL: vp_nearbyint_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -870,7 +870,7 @@ define <vscale x 2 x double> @vp_nearbyint_nxv2f64(<vscale x 2 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -892,7 +892,7 @@ define <vscale x 2 x double> @vp_nearbyint_nxv2f64_unmasked(<vscale x 2 x double
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -914,7 +914,7 @@ define <vscale x 4 x double> @vp_nearbyint_nxv4f64(<vscale x 4 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -936,7 +936,7 @@ define <vscale x 4 x double> @vp_nearbyint_nxv4f64_unmasked(<vscale x 4 x double
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -958,7 +958,7 @@ define <vscale x 7 x double> @vp_nearbyint_nxv7f64(<vscale x 7 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -980,7 +980,7 @@ define <vscale x 7 x double> @vp_nearbyint_nxv7f64_unmasked(<vscale x 7 x double
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1002,7 +1002,7 @@ define <vscale x 8 x double> @vp_nearbyint_nxv8f64(<vscale x 8 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -1024,7 +1024,7 @@ define <vscale x 8 x double> @vp_nearbyint_nxv8f64_unmasked(<vscale x 8 x double
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1056,7 +1056,7 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: frflags a2
@@ -1073,7 +1073,7 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: frflags a0
@@ -1100,7 +1100,7 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: frflags a2
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -1113,7 +1113,7 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
index 88bd92c6ec1612..955f2134c9fb3b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
@@ -180,7 +180,7 @@ define <vscale x 4 x half> @vp_rint_nxv4f16(<vscale x 4 x half> %va, <vscale x 4
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -217,7 +217,7 @@ define <vscale x 4 x half> @vp_rint_nxv4f16_unmasked(<vscale x 4 x half> %va, i3
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -241,7 +241,7 @@ define <vscale x 8 x half> @vp_rint_nxv8f16(<vscale x 8 x half> %va, <vscale x 8
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: vmv1r.v v0, v10
@@ -258,7 +258,7 @@ define <vscale x 8 x half> @vp_rint_nxv8f16(<vscale x 8 x half> %va, <vscale x 8
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -282,7 +282,7 @@ define <vscale x 8 x half> @vp_rint_nxv8f16_unmasked(<vscale x 8 x half> %va, i3
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -295,7 +295,7 @@ define <vscale x 8 x half> @vp_rint_nxv8f16_unmasked(<vscale x 8 x half> %va, i3
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -319,7 +319,7 @@ define <vscale x 16 x half> @vp_rint_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; ZVFH-NEXT: vmv1r.v v12, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
; ZVFH-NEXT: vmv1r.v v0, v12
@@ -336,7 +336,7 @@ define <vscale x 16 x half> @vp_rint_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -360,7 +360,7 @@ define <vscale x 16 x half> @vp_rint_nxv16f16_unmasked(<vscale x 16 x half> %va,
; ZVFH-NEXT: lui a1, %hi(.LCPI9_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -373,7 +373,7 @@ define <vscale x 16 x half> @vp_rint_nxv16f16_unmasked(<vscale x 16 x half> %va,
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -397,7 +397,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; ZVFH-NEXT: vmv1r.v v16, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v24, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
; ZVFH-NEXT: vmv1r.v v0, v16
@@ -432,7 +432,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -455,7 +455,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vmv1r.v v8, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v8
@@ -485,7 +485,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFH-NEXT: lui a1, %hi(.LCPI11_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -518,7 +518,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -539,7 +539,7 @@ define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -639,7 +639,7 @@ define <vscale x 4 x float> @vp_rint_nxv4f32(<vscale x 4 x float> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -659,7 +659,7 @@ define <vscale x 4 x float> @vp_rint_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vp_rint_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -679,7 +679,7 @@ define <vscale x 8 x float> @vp_rint_nxv8f32(<vscale x 8 x float> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -699,7 +699,7 @@ define <vscale x 8 x float> @vp_rint_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vp_rint_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -719,7 +719,7 @@ define <vscale x 16 x float> @vp_rint_nxv16f32(<vscale x 16 x float> %va, <vscal
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -739,7 +739,7 @@ define <vscale x 16 x float> @vp_rint_nxv16f32_unmasked(<vscale x 16 x float> %v
; CHECK-LABEL: vp_rint_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -799,7 +799,7 @@ define <vscale x 2 x double> @vp_rint_nxv2f64(<vscale x 2 x double> %va, <vscale
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
@@ -819,7 +819,7 @@ define <vscale x 2 x double> @vp_rint_nxv2f64_unmasked(<vscale x 2 x double> %va
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -839,7 +839,7 @@ define <vscale x 4 x double> @vp_rint_nxv4f64(<vscale x 4 x double> %va, <vscale
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
@@ -859,7 +859,7 @@ define <vscale x 4 x double> @vp_rint_nxv4f64_unmasked(<vscale x 4 x double> %va
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -879,7 +879,7 @@ define <vscale x 7 x double> @vp_rint_nxv7f64(<vscale x 7 x double> %va, <vscale
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
@@ -899,7 +899,7 @@ define <vscale x 7 x double> @vp_rint_nxv7f64_unmasked(<vscale x 7 x double> %va
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -919,7 +919,7 @@ define <vscale x 8 x double> @vp_rint_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
@@ -939,7 +939,7 @@ define <vscale x 8 x double> @vp_rint_nxv8f64_unmasked(<vscale x 8 x double> %va
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -975,7 +975,7 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
@@ -993,7 +993,7 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: vmv1r.v v0, v7
@@ -1022,7 +1022,7 @@ define <vscale x 16 x double> @vp_rint_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -1033,7 +1033,7 @@ define <vscale x 16 x double> @vp_rint_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
index 1ddadcc4937361..fefb9396f426bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
@@ -198,7 +198,7 @@ define <vscale x 4 x half> @vp_round_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <vscale x 4 x half> @vp_round_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <vscale x 8 x half> @vp_round_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 4
@@ -284,7 +284,7 @@ define <vscale x 8 x half> @vp_round_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <vscale x 8 x half> @vp_round_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <vscale x 8 x half> @vp_round_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -351,7 +351,7 @@ define <vscale x 16 x half> @vp_round_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; ZVFH-NEXT: vmv1r.v v12, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 4
@@ -370,7 +370,7 @@ define <vscale x 16 x half> @vp_round_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -396,7 +396,7 @@ define <vscale x 16 x half> @vp_round_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFH-NEXT: lui a1, %hi(.LCPI9_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -411,7 +411,7 @@ define <vscale x 16 x half> @vp_round_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -437,7 +437,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; ZVFH-NEXT: vmv1r.v v16, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v24, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 4
@@ -474,7 +474,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -499,7 +499,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v8, v16
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v8
@@ -534,7 +534,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH-NEXT: lui a1, %hi(.LCPI11_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -569,7 +569,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -592,7 +592,7 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -702,7 +702,7 @@ define <vscale x 4 x float> @vp_round_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -724,7 +724,7 @@ define <vscale x 4 x float> @vp_round_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vp_round_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -746,7 +746,7 @@ define <vscale x 8 x float> @vp_round_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -768,7 +768,7 @@ define <vscale x 8 x float> @vp_round_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vp_round_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -790,7 +790,7 @@ define <vscale x 16 x float> @vp_round_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -812,7 +812,7 @@ define <vscale x 16 x float> @vp_round_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-LABEL: vp_round_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -878,7 +878,7 @@ define <vscale x 2 x double> @vp_round_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -900,7 +900,7 @@ define <vscale x 2 x double> @vp_round_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -922,7 +922,7 @@ define <vscale x 4 x double> @vp_round_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -944,7 +944,7 @@ define <vscale x 4 x double> @vp_round_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -966,7 +966,7 @@ define <vscale x 7 x double> @vp_round_nxv7f64(<vscale x 7 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -988,7 +988,7 @@ define <vscale x 7 x double> @vp_round_nxv7f64_unmasked(<vscale x 7 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1010,7 +1010,7 @@ define <vscale x 8 x double> @vp_round_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -1032,7 +1032,7 @@ define <vscale x 8 x double> @vp_round_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1070,7 +1070,7 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a2, 4
@@ -1091,7 +1091,7 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
@@ -1122,7 +1122,7 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a2, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -1135,7 +1135,7 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
index 8c5a7bb2dea6aa..6626a1343beef7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
@@ -198,7 +198,7 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16(<vscale x 4 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16_unmasked(<vscale x 4 x half> %v
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 0
@@ -284,7 +284,7 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -351,7 +351,7 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; ZVFH-NEXT: vmv1r.v v12, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 0
@@ -370,7 +370,7 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -396,7 +396,7 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFH-NEXT: lui a1, %hi(.LCPI9_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -411,7 +411,7 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -437,7 +437,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; ZVFH-NEXT: vmv1r.v v16, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v24, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 0
@@ -474,7 +474,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -499,7 +499,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vmv1r.v v8, v16
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v8
@@ -534,7 +534,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFH-NEXT: lui a1, %hi(.LCPI11_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -569,7 +569,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -592,7 +592,7 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -702,7 +702,7 @@ define <vscale x 4 x float> @vp_roundeven_nxv4f32(<vscale x 4 x float> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -724,7 +724,7 @@ define <vscale x 4 x float> @vp_roundeven_nxv4f32_unmasked(<vscale x 4 x float>
; CHECK-LABEL: vp_roundeven_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -746,7 +746,7 @@ define <vscale x 8 x float> @vp_roundeven_nxv8f32(<vscale x 8 x float> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -768,7 +768,7 @@ define <vscale x 8 x float> @vp_roundeven_nxv8f32_unmasked(<vscale x 8 x float>
; CHECK-LABEL: vp_roundeven_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -790,7 +790,7 @@ define <vscale x 16 x float> @vp_roundeven_nxv16f32(<vscale x 16 x float> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -812,7 +812,7 @@ define <vscale x 16 x float> @vp_roundeven_nxv16f32_unmasked(<vscale x 16 x floa
; CHECK-LABEL: vp_roundeven_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -878,7 +878,7 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64(<vscale x 2 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -900,7 +900,7 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -922,7 +922,7 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64(<vscale x 4 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -944,7 +944,7 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -966,7 +966,7 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64(<vscale x 7 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -988,7 +988,7 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1010,7 +1010,7 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64(<vscale x 8 x double> %va, <v
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -1032,7 +1032,7 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1070,7 +1070,7 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a2, 0
@@ -1091,7 +1091,7 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
@@ -1122,7 +1122,7 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a2, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -1135,7 +1135,7 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
index 1227e73a024325..ccb737a5e908f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
@@ -198,7 +198,7 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16(<vscale x 4 x half> %va, <vsc
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v10, v10, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,7 +239,7 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16_unmasked(<vscale x 4 x half>
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v10, v10
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -265,7 +265,7 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16(<vscale x 8 x half> %va, <vsc
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
; ZVFH-NEXT: vmv1r.v v10, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 1
@@ -284,7 +284,7 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16(<vscale x 8 x half> %va, <vsc
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v12, v12, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -310,7 +310,7 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16_unmasked(<vscale x 8 x half>
; ZVFH-NEXT: lui a1, %hi(.LCPI7_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v10, v8
+; ZVFH-NEXT: vfsgnjx.vv v10, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -325,7 +325,7 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16_unmasked(<vscale x 8 x half>
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v12, v12
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -351,7 +351,7 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16(<vscale x 16 x half> %va, <
; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a1)
; ZVFH-NEXT: vmv1r.v v12, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 1
@@ -370,7 +370,7 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16(<vscale x 16 x half> %va, <
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -396,7 +396,7 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16_unmasked(<vscale x 16 x hal
; ZVFH-NEXT: lui a1, %hi(.LCPI9_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
+; ZVFH-NEXT: vfsgnjx.vv v12, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -411,7 +411,7 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16_unmasked(<vscale x 16 x hal
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v16, v16
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -437,7 +437,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16(<vscale x 32 x half> %va, <
; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a1)
; ZVFH-NEXT: vmv1r.v v16, v0
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v24, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
; ZVFH-NEXT: fsrmi a0, 1
@@ -474,7 +474,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16(<vscale x 32 x half> %va, <
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -499,7 +499,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16(<vscale x 32 x half> %va, <
; ZVFHMIN-NEXT: vmv1r.v v8, v16
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v8
@@ -534,7 +534,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
; ZVFH-NEXT: lui a1, %hi(.LCPI11_0)
; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a1)
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v16, v8
+; ZVFH-NEXT: vfsgnjx.vv v16, v8, v8
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -569,7 +569,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v8, v24, v24, v0.t
; ZVFHMIN-NEXT: lui a2, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -592,7 +592,7 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v16, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -702,7 +702,7 @@ define <vscale x 4 x float> @vp_roundtozero_nxv4f32(<vscale x 4 x float> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -724,7 +724,7 @@ define <vscale x 4 x float> @vp_roundtozero_nxv4f32_unmasked(<vscale x 4 x float
; CHECK-LABEL: vp_roundtozero_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
@@ -746,7 +746,7 @@ define <vscale x 8 x float> @vp_roundtozero_nxv8f32(<vscale x 8 x float> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -768,7 +768,7 @@ define <vscale x 8 x float> @vp_roundtozero_nxv8f32_unmasked(<vscale x 8 x float
; CHECK-LABEL: vp_roundtozero_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -790,7 +790,7 @@ define <vscale x 16 x float> @vp_roundtozero_nxv16f32(<vscale x 16 x float> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -812,7 +812,7 @@ define <vscale x 16 x float> @vp_roundtozero_nxv16f32_unmasked(<vscale x 16 x fl
; CHECK-LABEL: vp_roundtozero_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
@@ -878,7 +878,7 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64(<vscale x 2 x double> %va,
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -900,7 +900,7 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64_unmasked(<vscale x 2 x doub
; CHECK-NEXT: lui a1, %hi(.LCPI25_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
@@ -922,7 +922,7 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64(<vscale x 4 x double> %va,
; CHECK-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -944,7 +944,7 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64_unmasked(<vscale x 4 x doub
; CHECK-NEXT: lui a1, %hi(.LCPI27_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
@@ -966,7 +966,7 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64(<vscale x 7 x double> %va,
; CHECK-NEXT: fld fa5, %lo(.LCPI28_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -988,7 +988,7 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64_unmasked(<vscale x 7 x doub
; CHECK-NEXT: lui a1, %hi(.LCPI29_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI29_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1010,7 +1010,7 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64(<vscale x 8 x double> %va,
; CHECK-NEXT: fld fa5, %lo(.LCPI30_0)(a1)
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -1032,7 +1032,7 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64_unmasked(<vscale x 8 x doub
; CHECK-NEXT: lui a1, %hi(.LCPI31_0)
; CHECK-NEXT: fld fa5, %lo(.LCPI31_0)(a1)
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
@@ -1070,7 +1070,7 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a2, 1
@@ -1091,7 +1091,7 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
@@ -1122,7 +1122,7 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v16
+; CHECK-NEXT: vfsgnjx.vv v24, v16, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a2, 1
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
@@ -1135,7 +1135,7 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v24, v8
+; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, fa5
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index f25a3f937f1b4f..dd868f3f9268d2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -312,7 +312,7 @@ define <vscale x 16 x i8> @vandn_vv_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16
; CHECK-LABEL: vandn_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
;
@@ -330,7 +330,7 @@ define <vscale x 16 x i8> @vandn_vv_swapped_nxv16i8(<vscale x 16 x i8> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v10, v8
; CHECK-NEXT: ret
;
@@ -388,7 +388,7 @@ define <vscale x 32 x i8> @vandn_vv_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32
; CHECK-LABEL: vandn_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
;
@@ -406,7 +406,7 @@ define <vscale x 32 x i8> @vandn_vv_swapped_nxv32i8(<vscale x 32 x i8> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v12, v8
; CHECK-NEXT: ret
;
@@ -464,7 +464,7 @@ define <vscale x 64 x i8> @vandn_vv_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64
; CHECK-LABEL: vandn_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: ret
;
@@ -482,7 +482,7 @@ define <vscale x 64 x i8> @vandn_vv_swapped_nxv64i8(<vscale x 64 x i8> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v16, v8
; CHECK-NEXT: ret
;
@@ -768,7 +768,7 @@ define <vscale x 8 x i16> @vandn_vv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x
; CHECK-LABEL: vandn_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
;
@@ -786,7 +786,7 @@ define <vscale x 8 x i16> @vandn_vv_swapped_nxv8i16(<vscale x 8 x i16> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v10, v8
; CHECK-NEXT: ret
;
@@ -844,7 +844,7 @@ define <vscale x 16 x i16> @vandn_vv_nxv16i16(<vscale x 16 x i16> %x, <vscale x
; CHECK-LABEL: vandn_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
;
@@ -862,7 +862,7 @@ define <vscale x 16 x i16> @vandn_vv_swapped_nxv16i16(<vscale x 16 x i16> %x, <v
; CHECK-LABEL: vandn_vv_swapped_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v12, v8
; CHECK-NEXT: ret
;
@@ -920,7 +920,7 @@ define <vscale x 32 x i16> @vandn_vv_nxv32i16(<vscale x 32 x i16> %x, <vscale x
; CHECK-LABEL: vandn_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: ret
;
@@ -938,7 +938,7 @@ define <vscale x 32 x i16> @vandn_vv_swapped_nxv32i16(<vscale x 32 x i16> %x, <v
; CHECK-LABEL: vandn_vv_swapped_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v16, v8
; CHECK-NEXT: ret
;
@@ -1148,7 +1148,7 @@ define <vscale x 4 x i32> @vandn_vv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x
; CHECK-LABEL: vandn_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
;
@@ -1166,7 +1166,7 @@ define <vscale x 4 x i32> @vandn_vv_swapped_nxv4i32(<vscale x 4 x i32> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v10, v8
; CHECK-NEXT: ret
;
@@ -1224,7 +1224,7 @@ define <vscale x 8 x i32> @vandn_vv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x
; CHECK-LABEL: vandn_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
;
@@ -1242,7 +1242,7 @@ define <vscale x 8 x i32> @vandn_vv_swapped_nxv8i32(<vscale x 8 x i32> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v12, v8
; CHECK-NEXT: ret
;
@@ -1300,7 +1300,7 @@ define <vscale x 16 x i32> @vandn_vv_nxv16i32(<vscale x 16 x i32> %x, <vscale x
; CHECK-LABEL: vandn_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: ret
;
@@ -1318,7 +1318,7 @@ define <vscale x 16 x i32> @vandn_vv_swapped_nxv16i32(<vscale x 16 x i32> %x, <v
; CHECK-LABEL: vandn_vv_swapped_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v16, v8
; CHECK-NEXT: ret
;
@@ -1512,7 +1512,7 @@ define <vscale x 2 x i64> @vandn_vv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x
; CHECK-LABEL: vandn_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
;
@@ -1530,7 +1530,7 @@ define <vscale x 2 x i64> @vandn_vv_swapped_nxv2i64(<vscale x 2 x i64> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v10, v8
; CHECK-NEXT: ret
;
@@ -1648,7 +1648,7 @@ define <vscale x 4 x i64> @vandn_vv_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x
; CHECK-LABEL: vandn_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
;
@@ -1666,7 +1666,7 @@ define <vscale x 4 x i64> @vandn_vv_swapped_nxv4i64(<vscale x 4 x i64> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v12, v8
; CHECK-NEXT: ret
;
@@ -1784,7 +1784,7 @@ define <vscale x 8 x i64> @vandn_vv_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x
; CHECK-LABEL: vandn_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: ret
;
@@ -1802,7 +1802,7 @@ define <vscale x 8 x i64> @vandn_vv_swapped_nxv8i64(<vscale x 8 x i64> %x, <vsca
; CHECK-LABEL: vandn_vv_swapped_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: vand.vv v8, v16, v8
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
index 95866543828fc7..351420fe47123b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
@@ -247,7 +247,7 @@ define <vscale x 16 x i8> @vandn_vv_vp_nxv16i8(<vscale x 16 x i8> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
;
@@ -265,7 +265,7 @@ define <vscale x 16 x i8> @vandn_vv_vp_swapped_nxv16i8(<vscale x 16 x i8> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
;
@@ -306,7 +306,7 @@ define <vscale x 32 x i8> @vandn_vv_vp_nxv32i8(<vscale x 32 x i8> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
;
@@ -324,7 +324,7 @@ define <vscale x 32 x i8> @vandn_vv_vp_swapped_nxv32i8(<vscale x 32 x i8> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
;
@@ -365,7 +365,7 @@ define <vscale x 64 x i8> @vandn_vv_vp_nxv64i8(<vscale x 64 x i8> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
;
@@ -383,7 +383,7 @@ define <vscale x 64 x i8> @vandn_vv_vp_swapped_nxv64i8(<vscale x 64 x i8> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
;
@@ -601,7 +601,7 @@ define <vscale x 8 x i16> @vandn_vv_vp_nxv8i16(<vscale x 8 x i16> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
;
@@ -619,7 +619,7 @@ define <vscale x 8 x i16> @vandn_vv_vp_swapped_nxv8i16(<vscale x 8 x i16> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
;
@@ -660,7 +660,7 @@ define <vscale x 16 x i16> @vandn_vv_vp_nxv16i16(<vscale x 16 x i16> %a, <vscale
; CHECK-LABEL: vandn_vv_vp_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
;
@@ -678,7 +678,7 @@ define <vscale x 16 x i16> @vandn_vv_vp_swapped_nxv16i16(<vscale x 16 x i16> %a,
; CHECK-LABEL: vandn_vv_vp_swapped_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
;
@@ -719,7 +719,7 @@ define <vscale x 32 x i16> @vandn_vv_vp_nxv32i16(<vscale x 32 x i16> %a, <vscale
; CHECK-LABEL: vandn_vv_vp_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
;
@@ -737,7 +737,7 @@ define <vscale x 32 x i16> @vandn_vv_vp_swapped_nxv32i16(<vscale x 32 x i16> %a,
; CHECK-LABEL: vandn_vv_vp_swapped_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
;
@@ -896,7 +896,7 @@ define <vscale x 4 x i32> @vandn_vv_vp_nxv4i32(<vscale x 4 x i32> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
;
@@ -914,7 +914,7 @@ define <vscale x 4 x i32> @vandn_vv_vp_swapped_nxv4i32(<vscale x 4 x i32> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
;
@@ -955,7 +955,7 @@ define <vscale x 8 x i32> @vandn_vv_vp_nxv8i32(<vscale x 8 x i32> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
;
@@ -973,7 +973,7 @@ define <vscale x 8 x i32> @vandn_vv_vp_swapped_nxv8i32(<vscale x 8 x i32> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
;
@@ -1014,7 +1014,7 @@ define <vscale x 16 x i32> @vandn_vv_vp_nxv16i32(<vscale x 16 x i32> %a, <vscale
; CHECK-LABEL: vandn_vv_vp_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
;
@@ -1032,7 +1032,7 @@ define <vscale x 16 x i32> @vandn_vv_vp_swapped_nxv16i32(<vscale x 16 x i32> %a,
; CHECK-LABEL: vandn_vv_vp_swapped_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
;
@@ -1164,7 +1164,7 @@ define <vscale x 2 x i64> @vandn_vv_vp_nxv2i64(<vscale x 2 x i64> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
;
@@ -1182,7 +1182,7 @@ define <vscale x 2 x i64> @vandn_vv_vp_swapped_nxv2i64(<vscale x 2 x i64> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
;
@@ -1255,7 +1255,7 @@ define <vscale x 4 x i64> @vandn_vv_vp_nxv4i64(<vscale x 4 x i64> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
;
@@ -1273,7 +1273,7 @@ define <vscale x 4 x i64> @vandn_vv_vp_swapped_nxv4i64(<vscale x 4 x i64> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
;
@@ -1346,7 +1346,7 @@ define <vscale x 8 x i64> @vandn_vv_vp_nxv8i64(<vscale x 8 x i64> %a, <vscale x
; CHECK-LABEL: vandn_vv_vp_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
;
@@ -1364,7 +1364,7 @@ define <vscale x 8 x i64> @vandn_vv_vp_swapped_nxv8i64(<vscale x 8 x i64> %a, <v
; CHECK-LABEL: vandn_vv_vp_swapped_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
index 95a410ea56b74a..20a44bc520faed 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
@@ -66,7 +66,7 @@ define <vscale x 4 x half> @vfabs_nxv4f16(<vscale x 4 x half> %v) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -80,7 +80,7 @@ define <vscale x 8 x half> @vfabs_nxv8f16(<vscale x 8 x half> %v) {
; ZVFH-LABEL: vfabs_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_nxv8f16:
@@ -88,7 +88,7 @@ define <vscale x 8 x half> @vfabs_nxv8f16(<vscale x 8 x half> %v) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -102,7 +102,7 @@ define <vscale x 16 x half> @vfabs_nxv16f16(<vscale x 16 x half> %v) {
; ZVFH-LABEL: vfabs_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_nxv16f16:
@@ -110,7 +110,7 @@ define <vscale x 16 x half> @vfabs_nxv16f16(<vscale x 16 x half> %v) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -124,7 +124,7 @@ define <vscale x 32 x half> @vfabs_nxv32f16(<vscale x 32 x half> %v) {
; ZVFH-LABEL: vfabs_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_nxv32f16:
@@ -132,12 +132,12 @@ define <vscale x 32 x half> @vfabs_nxv32f16(<vscale x 32 x half> %v) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: ret
@@ -175,7 +175,7 @@ define <vscale x 4 x float> @vfabs_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-LABEL: vfabs_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %v)
ret <vscale x 4 x float> %r
@@ -187,7 +187,7 @@ define <vscale x 8 x float> @vfabs_nxv8f32(<vscale x 8 x float> %v) {
; CHECK-LABEL: vfabs_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float> %v)
ret <vscale x 8 x float> %r
@@ -199,7 +199,7 @@ define <vscale x 16 x float> @vfabs_nxv16f32(<vscale x 16 x float> %v) {
; CHECK-LABEL: vfabs_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float> %v)
ret <vscale x 16 x float> %r
@@ -223,7 +223,7 @@ define <vscale x 2 x double> @vfabs_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-LABEL: vfabs_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %v)
ret <vscale x 2 x double> %r
@@ -235,7 +235,7 @@ define <vscale x 4 x double> @vfabs_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-LABEL: vfabs_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %v)
ret <vscale x 4 x double> %r
@@ -247,7 +247,7 @@ define <vscale x 8 x double> @vfabs_nxv8f64(<vscale x 8 x double> %v) {
; CHECK-LABEL: vfabs_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double> %v)
ret <vscale x 8 x double> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index 0f7e3f1e0ea5a2..ce8bea899f2c14 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -106,7 +106,7 @@ define <vscale x 4 x half> @vfabs_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v10, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v10, v10, v10, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -126,7 +126,7 @@ define <vscale x 4 x half> @vfabs_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjx.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -140,7 +140,7 @@ define <vscale x 8 x half> @vfabs_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFH-LABEL: vfabs_vv_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv8f16:
@@ -148,7 +148,7 @@ define <vscale x 8 x half> @vfabs_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v12, v12, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -160,7 +160,7 @@ define <vscale x 8 x half> @vfabs_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFH-LABEL: vfabs_vv_nxv8f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv8f16_unmasked:
@@ -168,7 +168,7 @@ define <vscale x 8 x half> @vfabs_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjx.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -182,7 +182,7 @@ define <vscale x 16 x half> @vfabs_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-LABEL: vfabs_vv_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv16f16:
@@ -190,7 +190,7 @@ define <vscale x 16 x half> @vfabs_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -202,7 +202,7 @@ define <vscale x 16 x half> @vfabs_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFH-LABEL: vfabs_vv_nxv16f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv16f16_unmasked:
@@ -210,7 +210,7 @@ define <vscale x 16 x half> @vfabs_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -224,7 +224,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-LABEL: vfabs_vv_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv32f16:
@@ -242,7 +242,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v24, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v24, v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
; ZVFHMIN-NEXT: bltu a0, a1, .LBB10_2
@@ -252,7 +252,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -264,7 +264,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH-LABEL: vfabs_vv_nxv32f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfabs.v v8, v8
+; ZVFH-NEXT: vfsgnjx.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv32f16_unmasked:
@@ -283,7 +283,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
@@ -292,7 +292,7 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: .LBB11_2:
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjx.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -350,7 +350,7 @@ define <vscale x 4 x float> @vfabs_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-LABEL: vfabs_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x float> %v
@@ -360,7 +360,7 @@ define <vscale x 4 x float> @vfabs_vv_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfabs_vv_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x float> %v
@@ -372,7 +372,7 @@ define <vscale x 8 x float> @vfabs_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: vfabs_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x float> %v
@@ -382,7 +382,7 @@ define <vscale x 8 x float> @vfabs_vv_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfabs_vv_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x float> %v
@@ -394,7 +394,7 @@ define <vscale x 16 x float> @vfabs_vv_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK-LABEL: vfabs_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x float> %v
@@ -404,7 +404,7 @@ define <vscale x 16 x float> @vfabs_vv_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-LABEL: vfabs_vv_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x float> %v
@@ -438,7 +438,7 @@ define <vscale x 2 x double> @vfabs_vv_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-LABEL: vfabs_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
@@ -448,7 +448,7 @@ define <vscale x 2 x double> @vfabs_vv_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfabs_vv_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x double> %v
@@ -460,7 +460,7 @@ define <vscale x 4 x double> @vfabs_vv_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-LABEL: vfabs_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x double> %v
@@ -470,7 +470,7 @@ define <vscale x 4 x double> @vfabs_vv_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfabs_vv_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x double> %v
@@ -482,7 +482,7 @@ define <vscale x 7 x double> @vfabs_vv_nxv7f64(<vscale x 7 x double> %va, <vscal
; CHECK-LABEL: vfabs_vv_nxv7f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x double> %v
@@ -492,7 +492,7 @@ define <vscale x 7 x double> @vfabs_vv_nxv7f64_unmasked(<vscale x 7 x double> %v
; CHECK-LABEL: vfabs_vv_nxv7f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
ret <vscale x 7 x double> %v
@@ -504,7 +504,7 @@ define <vscale x 8 x double> @vfabs_vv_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-LABEL: vfabs_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x double> %v
@@ -514,7 +514,7 @@ define <vscale x 8 x double> @vfabs_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK-LABEL: vfabs_vv_nxv8f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x double> %v
@@ -536,14 +536,14 @@ define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v16, v0.t
+; CHECK-NEXT: vfsgnjx.vv v16, v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB32_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x double> %v
@@ -558,13 +558,13 @@ define <vscale x 16 x double> @vfabs_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v16
+; CHECK-NEXT: vfsgnjx.vv v16, v16, v16
; CHECK-NEXT: bltu a0, a1, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
index 029a121d08980c..83947338dd8e1f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
@@ -548,7 +548,7 @@ define <vscale x 4 x half> @vfcopynsign_vv_nxv4f16(<vscale x 4 x half> %vm, <vsc
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -579,7 +579,7 @@ define <vscale x 4 x half> @vfcopynsign_vf_nxv4f16(<vscale x 4 x half> %vm, half
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -658,7 +658,7 @@ define <vscale x 8 x half> @vfcopynsign_vv_nxv8f16(<vscale x 8 x half> %vm, <vsc
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -689,7 +689,7 @@ define <vscale x 8 x half> @vfcopynsign_vf_nxv8f16(<vscale x 8 x half> %vm, half
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -775,7 +775,7 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f32(<vscale x 8
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
@@ -809,7 +809,7 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f32(<vscale x 8
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
@@ -908,7 +908,7 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f64(<vscale x 8
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
@@ -947,7 +947,7 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f64(<vscale x 8
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
@@ -1026,7 +1026,7 @@ define <vscale x 16 x half> @vfcopynsign_vv_nxv16f16(<vscale x 16 x half> %vm, <
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
@@ -1057,7 +1057,7 @@ define <vscale x 16 x half> @vfcopynsign_vf_nxv16f16(<vscale x 16 x half> %vm, h
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
@@ -1147,12 +1147,12 @@ define <vscale x 32 x half> @vfcopynsign_vv_nxv32f16(<vscale x 32 x half> %vm, <
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v24, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v24, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v24, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v24, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
@@ -1189,7 +1189,7 @@ define <vscale x 32 x half> @vfcopynsign_vf_nxv32f16(<vscale x 32 x half> %vm, h
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
index c835dc72268b32..37583ca800eef5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
@@ -153,7 +153,7 @@ define <vscale x 4 x half> @vfmsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -185,7 +185,7 @@ define <vscale x 4 x half> @vfmsub_vf_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -217,7 +217,7 @@ define <vscale x 8 x half> @vfmsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
@@ -249,7 +249,7 @@ define <vscale x 8 x half> @vfmsub_vf_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
@@ -281,7 +281,7 @@ define <vscale x 16 x half> @vfmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v24, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v24, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
@@ -314,7 +314,7 @@ define <vscale x 16 x half> @vfmsub_vf_nxv16f16(<vscale x 16 x half> %va, <vscal
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
@@ -367,7 +367,7 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
; ZVFHMIN-NEXT: vmv4r.v v20, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
@@ -378,7 +378,7 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
@@ -451,7 +451,7 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
@@ -476,7 +476,7 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
index 21b895b812354a..b72f7f2677779c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
@@ -60,7 +60,7 @@ define <vscale x 4 x half> @vfneg_vv_nxv4f16(<vscale x 4 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -72,7 +72,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va) {
; ZVFH-LABEL: vfneg_vv_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv8f16:
@@ -80,7 +80,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -92,7 +92,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va) {
; ZVFH-LABEL: vfneg_vv_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv16f16:
@@ -100,7 +100,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -112,7 +112,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va) {
; ZVFH-LABEL: vfneg_vv_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv32f16:
@@ -120,12 +120,12 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: ret
@@ -157,7 +157,7 @@ define <vscale x 4 x float> @vfneg_vv_nxv4f32(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfneg_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 4 x float> %va
ret <vscale x 4 x float> %vb
@@ -167,7 +167,7 @@ define <vscale x 8 x float> @vfneg_vv_nxv8f32(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfneg_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 8 x float> %va
ret <vscale x 8 x float> %vb
@@ -177,7 +177,7 @@ define <vscale x 16 x float> @vfneg_vv_nxv16f32(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfneg_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 16 x float> %va
ret <vscale x 16 x float> %vb
@@ -197,7 +197,7 @@ define <vscale x 2 x double> @vfneg_vv_nxv2f64(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfneg_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 2 x double> %va
ret <vscale x 2 x double> %vb
@@ -207,7 +207,7 @@ define <vscale x 4 x double> @vfneg_vv_nxv4f64(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfneg_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 4 x double> %va
ret <vscale x 4 x double> %vb
@@ -217,7 +217,7 @@ define <vscale x 8 x double> @vfneg_vv_nxv8f64(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfneg_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%vb = fneg <vscale x 8 x double> %va
ret <vscale x 8 x double> %vb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index 69ea7ce33cf6b6..7e819ad6c41cec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -106,7 +106,7 @@ define <vscale x 4 x half> @vfneg_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -126,7 +126,7 @@ define <vscale x 4 x half> @vfneg_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
@@ -140,7 +140,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFH-LABEL: vfneg_vv_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv8f16:
@@ -148,7 +148,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -160,7 +160,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFH-LABEL: vfneg_vv_nxv8f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv8f16_unmasked:
@@ -168,7 +168,7 @@ define <vscale x 8 x half> @vfneg_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
@@ -182,7 +182,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-LABEL: vfneg_vv_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv16f16:
@@ -190,7 +190,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -202,7 +202,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFH-LABEL: vfneg_vv_nxv16f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv16f16_unmasked:
@@ -210,7 +210,7 @@ define <vscale x 16 x half> @vfneg_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -224,7 +224,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-LABEL: vfneg_vv_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8, v0.t
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv32f16:
@@ -242,7 +242,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v24, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v24, v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
; ZVFHMIN-NEXT: bltu a0, a1, .LBB10_2
@@ -252,7 +252,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -264,7 +264,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH-LABEL: vfneg_vv_nxv32f16_unmasked:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfneg.v v8, v8
+; ZVFH-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfneg_vv_nxv32f16_unmasked:
@@ -283,7 +283,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
@@ -292,7 +292,7 @@ define <vscale x 32 x half> @vfneg_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: .LBB11_2:
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: ret
@@ -350,7 +350,7 @@ define <vscale x 4 x float> @vfneg_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-LABEL: vfneg_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.fneg.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x float> %v
@@ -360,7 +360,7 @@ define <vscale x 4 x float> @vfneg_vv_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfneg_vv_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.fneg.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x float> %v
@@ -372,7 +372,7 @@ define <vscale x 8 x float> @vfneg_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: vfneg_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.fneg.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x float> %v
@@ -382,7 +382,7 @@ define <vscale x 8 x float> @vfneg_vv_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfneg_vv_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.fneg.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x float> %v
@@ -394,7 +394,7 @@ define <vscale x 16 x float> @vfneg_vv_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK-LABEL: vfneg_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x float> @llvm.vp.fneg.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x float> %v
@@ -404,7 +404,7 @@ define <vscale x 16 x float> @vfneg_vv_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-LABEL: vfneg_vv_nxv16f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 16 x float> @llvm.vp.fneg.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x float> %v
@@ -438,7 +438,7 @@ define <vscale x 2 x double> @vfneg_vv_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-LABEL: vfneg_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.fneg.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
@@ -448,7 +448,7 @@ define <vscale x 2 x double> @vfneg_vv_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfneg_vv_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.fneg.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x double> %v
@@ -460,7 +460,7 @@ define <vscale x 4 x double> @vfneg_vv_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-LABEL: vfneg_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.fneg.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x double> %v
@@ -470,7 +470,7 @@ define <vscale x 4 x double> @vfneg_vv_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfneg_vv_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.fneg.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x double> %v
@@ -482,7 +482,7 @@ define <vscale x 7 x double> @vfneg_vv_nxv7f64(<vscale x 7 x double> %va, <vscal
; CHECK-LABEL: vfneg_vv_nxv7f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x double> %v
@@ -492,7 +492,7 @@ define <vscale x 7 x double> @vfneg_vv_nxv7f64_unmasked(<vscale x 7 x double> %v
; CHECK-LABEL: vfneg_vv_nxv7f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
ret <vscale x 7 x double> %v
@@ -504,7 +504,7 @@ define <vscale x 8 x double> @vfneg_vv_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-LABEL: vfneg_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x double> %v
@@ -514,7 +514,7 @@ define <vscale x 8 x double> @vfneg_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK-LABEL: vfneg_vv_nxv8f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x double> %v
@@ -536,14 +536,14 @@ define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v16, v16, v0.t
+; CHECK-NEXT: vfsgnjn.vv v16, v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB32_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8, v0.t
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x double> %v
@@ -558,13 +558,13 @@ define <vscale x 16 x double> @vfneg_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v16, v16
+; CHECK-NEXT: vfsgnjn.vv v16, v16, v16
; CHECK-NEXT: bltu a0, a1, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
; CHECK-NEXT: ret
%v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
index b54590cd9d8440..fdc8bd3e8b89fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
@@ -177,12 +177,12 @@ define <vscale x 4 x half> @vfnmsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -215,12 +215,12 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -253,12 +253,12 @@ define <vscale x 8 x half> @vfnmsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
@@ -291,12 +291,12 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16(<vscale x 8 x half> %va, <vscale
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
@@ -330,12 +330,12 @@ define <vscale x 16 x half> @vfnmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4
@@ -369,12 +369,12 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
@@ -426,12 +426,12 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
@@ -456,7 +456,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -466,7 +466,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
@@ -532,7 +532,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -542,7 +542,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -562,7 +562,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
index 2f7e693a8a6f98..4f372b40595f59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
@@ -153,7 +153,7 @@ define <vscale x 4 x half> @vfnmsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
@@ -185,7 +185,7 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v10, v10
+; ZVFHMIN-NEXT: vfsgnjn.vv v10, v10, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
@@ -217,7 +217,7 @@ define <vscale x 8 x half> @vfnmsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
@@ -249,7 +249,7 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16(<vscale x 8 x half> %va, <vscale
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v12, v12
+; ZVFHMIN-NEXT: vfsgnjn.vv v12, v12, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -290,7 +290,7 @@ define <vscale x 16 x half> @vfnmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
@@ -337,7 +337,7 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v16, v16
+; ZVFHMIN-NEXT: vfsgnjn.vv v16, v16, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28
@@ -394,7 +394,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v0, v0
+; ZVFHMIN-NEXT: vfsgnjn.vv v0, v0, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
@@ -414,7 +414,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v8, v8
+; ZVFHMIN-NEXT: vfsgnjn.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -483,7 +483,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfneg.v v24, v24
+; ZVFHMIN-NEXT: vfsgnjn.vv v24, v24, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
index 3f10b10675ca70..2a0f23b9cb63a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
@@ -240,7 +240,7 @@ define <vscale x 16 x i8> @vxor_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vxor_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 16 x i8> %va, splat (i8 -1)
ret <vscale x 16 x i8> %vc
@@ -293,7 +293,7 @@ define <vscale x 32 x i8> @vxor_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vxor_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 32 x i8> %va, splat (i8 -1)
ret <vscale x 32 x i8> %vc
@@ -346,7 +346,7 @@ define <vscale x 64 x i8> @vxor_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vxor_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 64 x i8> %va, splat (i8 -1)
ret <vscale x 64 x i8> %vc
@@ -558,7 +558,7 @@ define <vscale x 8 x i16> @vxor_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vxor_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 8 x i16> %va, splat (i16 -1)
ret <vscale x 8 x i16> %vc
@@ -611,7 +611,7 @@ define <vscale x 16 x i16> @vxor_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vxor_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 16 x i16> %va, splat (i16 -1)
ret <vscale x 16 x i16> %vc
@@ -664,7 +664,7 @@ define <vscale x 32 x i16> @vxor_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vxor_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 32 x i16> %va, splat (i16 -1)
ret <vscale x 32 x i16> %vc
@@ -823,7 +823,7 @@ define <vscale x 4 x i32> @vxor_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vxor_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 4 x i32> %va, splat (i32 -1)
ret <vscale x 4 x i32> %vc
@@ -876,7 +876,7 @@ define <vscale x 8 x i32> @vxor_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vxor_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 8 x i32> %va, splat (i32 -1)
ret <vscale x 8 x i32> %vc
@@ -929,7 +929,7 @@ define <vscale x 16 x i32> @vxor_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vxor_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 16 x i32> %va, splat (i32 -1)
ret <vscale x 16 x i32> %vc
@@ -1061,7 +1061,7 @@ define <vscale x 2 x i64> @vxor_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vxor_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 2 x i64> %va, splat (i64 -1)
ret <vscale x 2 x i64> %vc
@@ -1127,7 +1127,7 @@ define <vscale x 4 x i64> @vxor_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vxor_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 4 x i64> %va, splat (i64 -1)
ret <vscale x 4 x i64> %vc
@@ -1193,7 +1193,7 @@ define <vscale x 8 x i64> @vxor_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vxor_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%vc = xor <vscale x 8 x i64> %va, splat (i64 -1)
ret <vscale x 8 x i64> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
index f2235b4fdc94ba..e04a61ad1744a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
@@ -432,7 +432,7 @@ define <vscale x 15 x i8> @vxor_vi_nxv15i8_1(<vscale x 15 x i8> %va, <vscale x 1
; CHECK-LABEL: vxor_vi_nxv15i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 -1), <vscale x 15 x i1> %m, i32 %evl)
ret <vscale x 15 x i8> %v
@@ -442,7 +442,7 @@ define <vscale x 15 x i8> @vxor_vi_nxv15i8_unmasked_1(<vscale x 15 x i8> %va, i3
; CHECK-LABEL: vxor_vi_nxv15i8_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 -1), <vscale x 15 x i1> splat (i1 true), i32 %evl)
ret <vscale x 15 x i8> %v
@@ -518,7 +518,7 @@ define <vscale x 16 x i8> @vxor_vi_nxv16i8_1(<vscale x 16 x i8> %va, <vscale x 1
; CHECK-LABEL: vxor_vi_nxv16i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -528,7 +528,7 @@ define <vscale x 16 x i8> @vxor_vi_nxv16i8_unmasked_1(<vscale x 16 x i8> %va, i3
; CHECK-LABEL: vxor_vi_nxv16i8_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i8> %v
@@ -604,7 +604,7 @@ define <vscale x 32 x i8> @vxor_vi_nxv32i8_1(<vscale x 32 x i8> %va, <vscale x 3
; CHECK-LABEL: vxor_vi_nxv32i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -614,7 +614,7 @@ define <vscale x 32 x i8> @vxor_vi_nxv32i8_unmasked_1(<vscale x 32 x i8> %va, i3
; CHECK-LABEL: vxor_vi_nxv32i8_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i8> %v
@@ -690,7 +690,7 @@ define <vscale x 64 x i8> @vxor_vi_nxv64i8_1(<vscale x 64 x i8> %va, <vscale x 6
; CHECK-LABEL: vxor_vi_nxv64i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -700,7 +700,7 @@ define <vscale x 64 x i8> @vxor_vi_nxv64i8_unmasked_1(<vscale x 64 x i8> %va, i3
; CHECK-LABEL: vxor_vi_nxv64i8_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i8> %v
@@ -1046,7 +1046,7 @@ define <vscale x 8 x i16> @vxor_vi_nxv8i16_1(<vscale x 8 x i16> %va, <vscale x 8
; CHECK-LABEL: vxor_vi_nxv8i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -1056,7 +1056,7 @@ define <vscale x 8 x i16> @vxor_vi_nxv8i16_unmasked_1(<vscale x 8 x i16> %va, i3
; CHECK-LABEL: vxor_vi_nxv8i16_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i16> %v
@@ -1132,7 +1132,7 @@ define <vscale x 16 x i16> @vxor_vi_nxv16i16_1(<vscale x 16 x i16> %va, <vscale
; CHECK-LABEL: vxor_vi_nxv16i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -1142,7 +1142,7 @@ define <vscale x 16 x i16> @vxor_vi_nxv16i16_unmasked_1(<vscale x 16 x i16> %va,
; CHECK-LABEL: vxor_vi_nxv16i16_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i16> %v
@@ -1218,7 +1218,7 @@ define <vscale x 32 x i16> @vxor_vi_nxv32i16_1(<vscale x 32 x i16> %va, <vscale
; CHECK-LABEL: vxor_vi_nxv32i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1228,7 +1228,7 @@ define <vscale x 32 x i16> @vxor_vi_nxv32i16_unmasked_1(<vscale x 32 x i16> %va,
; CHECK-LABEL: vxor_vi_nxv32i16_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1476,7 +1476,7 @@ define <vscale x 4 x i32> @vxor_vi_nxv4i32_1(<vscale x 4 x i32> %va, <vscale x 4
; CHECK-LABEL: vxor_vi_nxv4i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1486,7 +1486,7 @@ define <vscale x 4 x i32> @vxor_vi_nxv4i32_unmasked_1(<vscale x 4 x i32> %va, i3
; CHECK-LABEL: vxor_vi_nxv4i32_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1562,7 +1562,7 @@ define <vscale x 8 x i32> @vxor_vi_nxv8i32_1(<vscale x 8 x i32> %va, <vscale x 8
; CHECK-LABEL: vxor_vi_nxv8i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1572,7 +1572,7 @@ define <vscale x 8 x i32> @vxor_vi_nxv8i32_unmasked_1(<vscale x 8 x i32> %va, i3
; CHECK-LABEL: vxor_vi_nxv8i32_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1648,7 +1648,7 @@ define <vscale x 16 x i32> @vxor_vi_nxv16i32_1(<vscale x 16 x i32> %va, <vscale
; CHECK-LABEL: vxor_vi_nxv16i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1658,7 +1658,7 @@ define <vscale x 16 x i32> @vxor_vi_nxv16i32_unmasked_1(<vscale x 16 x i32> %va,
; CHECK-LABEL: vxor_vi_nxv16i32_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1876,7 +1876,7 @@ define <vscale x 2 x i64> @vxor_vi_nxv2i64_1(<vscale x 2 x i64> %va, <vscale x 2
; CHECK-LABEL: vxor_vi_nxv2i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1886,7 +1886,7 @@ define <vscale x 2 x i64> @vxor_vi_nxv2i64_unmasked_1(<vscale x 2 x i64> %va, i3
; CHECK-LABEL: vxor_vi_nxv2i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1990,7 +1990,7 @@ define <vscale x 4 x i64> @vxor_vi_nxv4i64_1(<vscale x 4 x i64> %va, <vscale x 4
; CHECK-LABEL: vxor_vi_nxv4i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -2000,7 +2000,7 @@ define <vscale x 4 x i64> @vxor_vi_nxv4i64_unmasked_1(<vscale x 4 x i64> %va, i3
; CHECK-LABEL: vxor_vi_nxv4i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i64> %v
@@ -2104,7 +2104,7 @@ define <vscale x 8 x i64> @vxor_vi_nxv8i64_1(<vscale x 8 x i64> %va, <vscale x 8
; CHECK-LABEL: vxor_vi_nxv8i64_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: vxor.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -2114,7 +2114,7 @@ define <vscale x 8 x i64> @vxor_vi_nxv8i64_unmasked_1(<vscale x 8 x i64> %va, i3
; CHECK-LABEL: vxor_vi_nxv8i64_unmasked_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vnot.v v8, v8
+; CHECK-NEXT: vxor.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i64> %v
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