[llvm] 6b27a57 - [RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-09T12:10:34-07:00
New Revision: 6b27a57d022aacd9067a953f9f8ce19acb13f475

URL: https://github.com/llvm/llvm-project/commit/6b27a57d022aacd9067a953f9f8ce19acb13f475
DIFF: https://github.com/llvm/llvm-project/commit/6b27a57d022aacd9067a953f9f8ce19acb13f475.diff

LOG: [RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir
new file mode 100644
index 00000000000000..ff5740feee8130
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV32I %s
+
+---
+name:            ctlz_s32
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: ctlz_s32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[CLZ:%[0-9]+]]:gpr = CLZ [[COPY]]
+    ; RV32I-NEXT: $x10 = COPY [[CLZ]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = G_CTLZ %0
+    $x10 = COPY %1(s32)
+    PseudoRET implicit $x10
+
+...

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
new file mode 100644
index 00000000000000..8c75bdd38d732a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV64I %s
+
+---
+name:            ctlz_s32
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: ctlz_s32
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]]
+    ; RV64I-NEXT: $x10 = COPY [[CLZW]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s32) = G_TRUNC %0
+    %2:gprb(s32) = G_CTLZ %1
+    %3:gprb(s64) = G_ANYEXT %2
+    $x10 = COPY %3(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            ctlz_s64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: ctlz_s64
+    ; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]]
+    ; RV64I-NEXT: $x10 = COPY [[CLZ]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = G_CTLZ %1
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir
new file mode 100644
index 00000000000000..f9ebd0bca51e8d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV32I %s
+
+---
+name:            cttz_s32
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: cttz_s32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[CTZ:%[0-9]+]]:gpr = CTZ [[COPY]]
+    ; RV32I-NEXT: $x10 = COPY [[CTZ]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = G_CTTZ %0
+    $x10 = COPY %1(s32)
+    PseudoRET implicit $x10
+
+...

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
new file mode 100644
index 00000000000000..b56d45f0993ada
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV64I %s
+
+---
+name:            cttz_s32
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: cttz_s32
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[CTZW:%[0-9]+]]:gpr = CTZW [[COPY]]
+    ; RV64I-NEXT: $x10 = COPY [[CTZW]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s32) = G_TRUNC %0
+    %2:gprb(s32) = G_CTTZ %1
+    %3:gprb(s64) = G_ANYEXT %2
+    $x10 = COPY %3(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            cttz_s64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: cttz_s64
+    ; RV64I: [[CTZ:%[0-9]+]]:gpr = CTZ [[CTZ]]
+    ; RV64I-NEXT: $x10 = COPY [[CTZ]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = G_CTTZ %1
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...