[llvm] e711a0c - [MIPS] Fix missing ANDI optimization (#97689)

[via llvm-commits]

Author: yingopq
Date: 2024-08-09T18:55:21+01:00
New Revision: e711a0c80fdd318afe869b7ddc16053dd2066d66

URL: https://github.com/llvm/llvm-project/commit/e711a0c80fdd318afe869b7ddc16053dd2066d66
DIFF: https://github.com/llvm/llvm-project/commit/e711a0c80fdd318afe869b7ddc16053dd2066d66.diff

LOG: [MIPS] Fix missing ANDI optimization (#97689)

1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi
(truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate
(dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fixes https://github.com/llvm/llvm-project/issues/42826

Added: 
    

Modified: 
    llvm/lib/Target/Mips/Mips64InstrInfo.td
    llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index f6ac3091a3ba8e..cb9a0d44a7a72b 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -830,6 +830,12 @@ def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
               ISA_MIPS3, GPR_64;
+def : MipsPat<(and (srl (i32 (trunc GPR64:$src)), immZExt5:$imm5), immZExt16:$value),
+              (ANDi (EXTRACT_SUBREG (DSRL GPR64:$src, immZExt5:$imm5), sub_32), immZExt16:$value)>,
+              ISA_MIPS3, GPR_64;
+def : MipsPat<(MipsExt (i32 (trunc GPR64:$src)), immZExt5:$pos, immZExt5:$size),
+              (EXTRACT_SUBREG (DEXT GPR64:$src, immZExt5:$pos, immZExt5:$size), sub_32)>,
+              ISA_MIPS3, GPR_64;
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)),

diff  --git a/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
index 988a0f5ee5ba3a..d154f13c8b59dd 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
@@ -6,8 +6,7 @@
 define i64 @foo(i64 noundef %a) {
 ; MIPS4-LABEL: foo:
 ; MIPS4:       # %bb.0: # %entry
-; MIPS4-NEXT:   sll    $1, $4, 0
-; MIPS4-NEXT:   srl    $1, $1, 2
+; MIPS4-NEXT:   dsrl   $1, $4, 2
 ; MIPS4-NEXT:   andi   $1, $1, 7
 ; MIPS4-NEXT:   daddiu $2, $zero, 1
 ; MIPS4-NEXT:   jr     $ra
@@ -15,8 +14,7 @@ define i64 @foo(i64 noundef %a) {
 ;
 ; MIPS64R2-LABEL: foo:
 ; MIPS64R2:       # %bb.0: # %entry
-; MIPS64R2-NEXT:   sll	  $1, $4, 0
-; MIPS64R2-NEXT:   ext	  $1, $1, 2, 3
+; MIPS64R2-NEXT:   dext	  $1, $4, 2, 3
 ; MIPS64R2-NEXT:   daddiu $2, $zero, 1
 ; MIPS64R2-NEXT:   jr     $ra
 ; MIPS64R2-NEXT:   dsllv  $2, $2, $1