[llvm] [AMDGPU][CodeGen] Support AND/OR/XOR and LDEXP True16 format (PR #102620)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff ae059a1f9f1e501b08a99cb636ec0869ec204c6f c8979269367a09977ed3016bbbec2cba03771679 --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
``````````

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<details>
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 40fbf428f1..987b484e7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -161,31 +161,34 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
 
         // TODO: Skip masking high bits if def is known boolean.
 
-		if (AMDGPU::getRegBitWidth(SrcRC->getID()) == 16) {
+        if (AMDGPU::getRegBitWidth(SrcRC->getID()) == 16) {
           assert(Subtarget->useRealTrue16Insts());
           const int64_t NoMods = 0;
           BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_AND_B16_t16_e64), MaskedReg)
-              .addImm(NoMods).addImm(1)
-              .addImm(NoMods).addReg(SrcReg)
+              .addImm(NoMods)
+              .addImm(1)
+              .addImm(NoMods)
+              .addReg(SrcReg)
               .addImm(NoMods);
           BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U16_t16_e64), DstReg)
-              .addImm(NoMods).addImm(0)
-              .addImm(NoMods).addReg(MaskedReg)
+              .addImm(NoMods)
+              .addImm(0)
+              .addImm(NoMods)
+              .addReg(MaskedReg)
               .addImm(NoMods);
         } else {
-			bool IsSGPR = TRI.isSGPRClass(SrcRC);
-			unsigned AndOpc =
-				IsSGPR ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;
-			auto And = BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg)
-				.addImm(1)
-				.addReg(SrcReg);
-			if (IsSGPR)
-			  And.setOperandDead(3); // Dead scc
-
-			BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
-				.addImm(0)
-				.addReg(MaskedReg);
-		}
+          bool IsSGPR = TRI.isSGPRClass(SrcRC);
+          unsigned AndOpc = IsSGPR ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;
+          auto And = BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg)
+                         .addImm(1)
+                         .addReg(SrcReg);
+          if (IsSGPR)
+            And.setOperandDead(3); // Dead scc
+
+          BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
+              .addImm(0)
+              .addReg(MaskedReg);
+        }
       }
 
       if (!MRI->getRegClassOrNull(SrcReg))

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https://github.com/llvm/llvm-project/pull/102620