[llvm] [llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (PR #102578)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 9 00:26:19 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-nvptx
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/102578.diff
15 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (+1-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+8-8)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+3-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (+1-1)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+2-2)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f827eb559a01cf..f0c459d61a4d74 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15720,7 +15720,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
// Finally, recreate the node, it's operands were updated to use
// frozen operands, so we just need to use it's "original" operands.
- SmallVector<SDValue> Ops(N0->op_begin(), N0->op_end());
+ SmallVector<SDValue> Ops(N0->ops());
// Special-handle ISD::UNDEF, each single one of them can be it's own thing.
for (SDValue &Op : Ops) {
if (Op.getOpcode() == ISD::UNDEF)
@@ -24160,7 +24160,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
!(LegalDAG && In.getValueType().isScalableVector())) {
unsigned NumOps = N->getNumOperands() * In.getNumOperands();
- SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
+ SmallVector<SDValue, 4> Ops(In->ops());
Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType()));
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
}
@@ -26612,7 +26612,7 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
N0.getOperand(0).getValueType().isScalableVector() ==
N1.getValueType().isScalableVector()) {
unsigned Factor = N1.getValueType().getVectorMinNumElements();
- SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
+ SmallVector<SDValue, 8> Ops(N0->ops());
Ops[InsIdx / Factor] = N1;
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bdb7917073020b..0150c5a2e90ed3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1449,8 +1449,7 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
// We introduced a cycle though, so update the loads operands, making sure
// to use the original store's chain as an incoming chain.
- SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
- NewLoad->op_end());
+ SmallVector<SDValue, 6> NewLoadOperands(NewLoad->ops());
NewLoadOperands[0] = Ch;
NewLoad =
SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 6c2b1743f462b5..ee411a74b2d30b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2375,7 +2375,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
// The Mask. Update in place.
EVT DataVT = DataOp.getValueType();
Mask = PromoteTargetBoolean(Mask, DataVT);
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
NewOps[4] = Mask;
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
}
@@ -2394,7 +2394,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
assert(OpNo == 3 && "Only know how to promote the mask!");
EVT DataVT = N->getValueType(0);
SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
NewOps[OpNo] = Mask;
SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
if (Res == N)
@@ -2408,7 +2408,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
unsigned OpNo) {
- SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 5> NewOps(N->ops());
if (OpNo == 2) {
// The Mask
@@ -2437,7 +2437,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
unsigned OpNo) {
bool TruncateStore = N->isTruncatingStore();
- SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 5> NewOps(N->ops());
if (OpNo == 2) {
// The Mask
@@ -2670,7 +2670,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
SDLoc DL(N);
SDValue Op = N->getOperand(OpNo);
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
if (OpNo == 2) { // Mask
// Update in place.
@@ -2726,14 +2726,14 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
(N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
- SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 8> NewOps(N->ops());
NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
}
SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
- SmallVector<SDValue, 6> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 6> NewOps(N->ops());
if (OpNo == 2) { // Offset operand
NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
@@ -5702,7 +5702,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
(N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
SDValue Hi; // The upper half is dropped out.
- SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 8> NewOps(N->ops());
GetExpandedInteger(NewOps[OpNo], NewOps[OpNo], Hi);
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cac8027f8760fa..5a21ad7ac7e2cd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5174,7 +5174,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_XRINT(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
SDValue InOp = N->getOperand(1);
SDLoc DL(N);
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
@@ -5469,7 +5469,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 16> NewOps(N->ops());
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
@@ -6664,7 +6664,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
unsigned NumElts = VT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(NumElts);
if (N->isStrictFPOpcode()) {
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
SmallVector<SDValue, 32> OpChains;
for (unsigned i=0; i < NumElts; ++i) {
NewOps[1] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index f44added89a728..53dd71d173473c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -143,7 +143,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
// Helper for AddGlue to clone node operands.
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
SDValue ExtraOper = SDValue()) {
- SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 8> Ops(N->ops());
if (ExtraOper.getNode())
Ops.push_back(ExtraOper);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bef70dcb71f567..866fac092792f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3245,7 +3245,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
// Don't simplify BROADCASTS.
if (llvm::any_of(Op->op_values(),
[&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
- SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
+ SmallVector<SDValue, 32> Ops(Op->ops());
bool Updated = false;
for (unsigned i = 0; i != NumElts; ++i) {
if (!DemandedElts[i] && !Ops[i].isUndef()) {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f0c3afc4f9b5d5..614128125af54f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14546,7 +14546,7 @@ SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op,
return Op;
// Concat each pair of subvectors and pack into the lower half of the array.
- SmallVector<SDValue> ConcatOps(Op->op_begin(), Op->op_end());
+ SmallVector<SDValue> ConcatOps(Op->ops());
while (ConcatOps.size() > 1) {
for (unsigned I = 0, E = ConcatOps.size(); I != E; I += 2) {
SDValue V1 = ConcatOps[I];
@@ -25040,7 +25040,7 @@ static SDValue legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) {
// Extend the unpacked offset vector to 64-bit lanes.
SDLoc DL(N);
Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset);
- SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 5> Ops(N->ops());
// Replace the offset operand with the 64-bit one.
Ops[OffsetPos] = Offset;
@@ -25060,7 +25060,7 @@ static SDValue combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG,
return SDValue();
// ...otherwise swap the offset base with the offset...
- SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 5> Ops(N->ops());
std::swap(Ops[ImmPos], Ops[OffsetPos]);
// ...and remap the intrinsic `aarch64_sve_prf<T>_gather_scalar_offset` to
// `aarch64_sve_prfb_gather_uxtw_index`.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index e36ec9595e85a2..8579774f522309 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2788,7 +2788,7 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
}
if (ConvGlueNode) {
- SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> NewOps(N->ops());
NewOps.push_back(SDValue(ConvGlueNode, 0));
CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), NewOps);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3fc02c6da37cb8..c82d1e26899785 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4957,7 +4957,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
SDValue CastBack =
DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi);
- SmallVector<SDValue, 8> Ops(BCSrc->op_begin(), BCSrc->op_end());
+ SmallVector<SDValue, 8> Ops(BCSrc->ops());
Ops.back() = CastBack;
DCI.AddToWorklist(NegHi.getNode());
SDValue Build =
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f8767e00949bf0..1cf9fb7a3724b7 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11383,7 +11383,7 @@ SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), N->getAddressSpace(),
N->getMemoryVT(), DCI);
if (NewPtr) {
- SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 8> NewOps(N->ops());
NewOps[PtrIdx] = NewPtr;
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
@@ -15103,7 +15103,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
} else
break;
- SmallVector<SDValue, 9> Ops(Node->op_begin(), Node->op_end());
+ SmallVector<SDValue, 9> Ops(Node->ops());
Ops[1] = Src0;
Ops[3] = Src1;
Ops[5] = Src2;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 75d16a42d0205a..8b65944c76ed63 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -9210,7 +9210,7 @@ static SDValue LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG,
};
// Concat each pair of subvectors and pack into the lower half of the array.
- SmallVector<SDValue> ConcatOps(Op->op_begin(), Op->op_end());
+ SmallVector<SDValue> ConcatOps(Op->ops());
while (ConcatOps.size() > 1) {
for (unsigned I = 0, E = ConcatOps.size(); I != E; I += 2) {
SDValue V1 = ConcatOps[I];
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 516fc7339a4bf3..800f2ba693f53b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -6143,7 +6143,7 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
}
// Copy regular operands
- SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 8> OtherOps(N->ops());
// The select routine does not have access to the LoadSDNode instance, so
// pass along the extension information
@@ -6300,7 +6300,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
"Custom handling of non-i8 ldu/ldg?");
// Just copy all operands as-is
- SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> Ops(N->ops());
// Force output to i16
SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 96e6c2ecf479bb..f1231b2b9baba2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14344,8 +14344,7 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
continue;
}
- SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
- PromOp.getNode()->op_end());
+ SmallVector<SDValue, 3> Ops(PromOp.getNode()->ops());
// If there are any constant inputs, make sure they're replaced now.
for (unsigned i = 0; i < 2; ++i)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b7a1a27a0f69c7..d8451a69d99272 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4080,7 +4080,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
// of the component build_vectors. We eagerly lower to scalable and
// insert_subvector here to avoid DAG combining it back to a large
// build_vector.
- SmallVector<SDValue> BuildVectorOps(Op->op_begin(), Op->op_end());
+ SmallVector<SDValue> BuildVectorOps(Op->ops());
unsigned NumOpElts = M1VT.getVectorMinNumElements();
SDValue Vec = DAG.getUNDEF(ContainerVT);
for (unsigned i = 0; i < VT.getVectorNumElements(); i += ElemsPerVReg) {
@@ -8782,7 +8782,7 @@ static SDValue lowerVectorIntrinsicScalars(SDValue Op, SelectionDAG &DAG,
unsigned SplatOp = II->ScalarOperand + 1 + HasChain;
assert(SplatOp < Op.getNumOperands());
- SmallVector<SDValue, 8> Operands(Op->op_begin(), Op->op_end());
+ SmallVector<SDValue, 8> Operands(Op->ops());
SDValue &ScalarOp = Operands[SplatOp];
MVT OpVT = ScalarOp.getSimpleValueType();
MVT XLenVT = Subtarget.getXLenVT();
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f69606783f25c8..f1bd002e1be3a5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -43938,7 +43938,7 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
if (ISD::isBuildVectorAllZeros(LastOp.getNode())) {
SrcVT = LastOp.getValueType();
unsigned NumConcats = 8 / SrcVT.getVectorNumElements();
- SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end());
+ SmallVector<SDValue, 4> Ops(N0->ops());
Ops.resize(NumConcats, DAG.getConstant(0, dl, SrcVT));
N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
N0 = DAG.getBitcast(MVT::i8, N0);
@@ -56793,7 +56793,7 @@ static SDValue combineCONCAT_VECTORS(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
EVT SrcVT = N->getOperand(0).getValueType();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
+ SmallVector<SDValue, 4> Ops(N->ops());
if (VT.getVectorElementType() == MVT::i1) {
// Attempt to constant fold.
``````````
</details>
https://github.com/llvm/llvm-project/pull/102578
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