[llvm] 0a4e1c5 - [RISCV] Add some Zfinx instructions to hasAllNBitUsers.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 8 17:41:34 PDT 2024
Author: Craig Topper
Date: 2024-08-08T17:33:54-07:00
New Revision: 0a4e1c518bbca5f3bced6ded6dd71d2fe6622ac3
URL: https://github.com/llvm/llvm-project/commit/0a4e1c518bbca5f3bced6ded6dd71d2fe6622ac3
DIFF: https://github.com/llvm/llvm-project/commit/0a4e1c518bbca5f3bced6ded6dd71d2fe6622ac3.diff
LOG: [RISCV] Add some Zfinx instructions to hasAllNBitUsers.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
llvm/test/CodeGen/RISCV/double-convert-strict.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert-strict.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/half-convert-strict.ll
llvm/test/CodeGen/RISCV/half-convert.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 604234b243153c..ce3a37e194d545 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3194,11 +3194,17 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::SLLI_UW:
case RISCV::FMV_W_X:
case RISCV::FCVT_H_W:
+ case RISCV::FCVT_H_W_INX:
case RISCV::FCVT_H_WU:
+ case RISCV::FCVT_H_WU_INX:
case RISCV::FCVT_S_W:
+ case RISCV::FCVT_S_W_INX:
case RISCV::FCVT_S_WU:
+ case RISCV::FCVT_S_WU_INX:
case RISCV::FCVT_D_W:
+ case RISCV::FCVT_D_W_INX:
case RISCV::FCVT_D_WU:
+ case RISCV::FCVT_D_WU_INX:
case RISCV::TH_REVW:
case RISCV::TH_SRRIW:
if (Bits >= 32)
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 00ac8cb9a9066d..effec2cc776d80 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -174,11 +174,17 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
case RISCV::SLLI_UW:
case RISCV::FMV_W_X:
case RISCV::FCVT_H_W:
+ case RISCV::FCVT_H_W_INX:
case RISCV::FCVT_H_WU:
+ case RISCV::FCVT_H_WU_INX:
case RISCV::FCVT_S_W:
+ case RISCV::FCVT_S_W_INX:
case RISCV::FCVT_S_WU:
+ case RISCV::FCVT_S_WU_INX:
case RISCV::FCVT_D_W:
+ case RISCV::FCVT_D_W_INX:
case RISCV::FCVT_D_WU:
+ case RISCV::FCVT_D_WU_INX:
if (Bits >= 32)
break;
return false;
diff --git a/llvm/test/CodeGen/RISCV/double-convert-strict.ll b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
index 13bcafb5ebd136..3732978b8bd83e 100644
--- a/llvm/test/CodeGen/RISCV/double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
@@ -777,11 +777,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
-; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
-; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
-; RV64IZFINXZDINX-NEXT: mv a0, a2
+; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
+; RV64IZFINXZDINX-NEXT: fcvt.d.w a2, a0
+; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index feea4f19720b0b..2e2e1b924cf009 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -1459,11 +1459,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
-; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
-; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
-; RV64IZFINXZDINX-NEXT: mv a0, a2
+; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
+; RV64IZFINXZDINX-NEXT: fcvt.d.w a2, a0
+; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
index 402d6f0362e6d3..0c265e11652a2e 100644
--- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
@@ -645,11 +645,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri
;
; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
; RV64IZFINX: # %bb.0:
-; RV64IZFINX-NEXT: addiw a2, a0, 1
-; RV64IZFINX-NEXT: addi a0, a0, 1
-; RV64IZFINX-NEXT: fcvt.s.w a0, a0
-; RV64IZFINX-NEXT: sw a0, 0(a1)
-; RV64IZFINX-NEXT: mv a0, a2
+; RV64IZFINX-NEXT: addiw a0, a0, 1
+; RV64IZFINX-NEXT: fcvt.s.w a2, a0
+; RV64IZFINX-NEXT: sw a2, 0(a1)
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 7eabd3f5f2273a..21bf6618c52a26 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -1247,11 +1247,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
;
; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
; RV64IZFINX: # %bb.0:
-; RV64IZFINX-NEXT: addiw a2, a0, 1
-; RV64IZFINX-NEXT: addi a0, a0, 1
-; RV64IZFINX-NEXT: fcvt.s.w a0, a0
-; RV64IZFINX-NEXT: sw a0, 0(a1)
-; RV64IZFINX-NEXT: mv a0, a2
+; RV64IZFINX-NEXT: addiw a0, a0, 1
+; RV64IZFINX-NEXT: fcvt.s.w a2, a0
+; RV64IZFINX-NEXT: sw a2, 0(a1)
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 677aa9263ea615..8f88a4c570ea05 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -1963,11 +1963,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
;
; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: addiw a2, a0, 1
-; RV64IZHINX-NEXT: addi a0, a0, 1
-; RV64IZHINX-NEXT: fcvt.h.w a0, a0
-; RV64IZHINX-NEXT: sh a0, 0(a1)
-; RV64IZHINX-NEXT: mv a0, a2
+; RV64IZHINX-NEXT: addiw a0, a0, 1
+; RV64IZHINX-NEXT: fcvt.h.w a2, a0
+; RV64IZHINX-NEXT: sh a2, 0(a1)
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
@@ -1993,11 +1991,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
;
; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: addiw a2, a0, 1
-; RV64IZDINXZHINX-NEXT: addi a0, a0, 1
-; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
-; RV64IZDINXZHINX-NEXT: sh a0, 0(a1)
-; RV64IZDINXZHINX-NEXT: mv a0, a2
+; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1
+; RV64IZDINXZHINX-NEXT: fcvt.h.w a2, a0
+; RV64IZDINXZHINX-NEXT: sh a2, 0(a1)
; RV64IZDINXZHINX-NEXT: ret
;
; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 31fb6e2ee9c840..48bfe1c37c625c 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -5760,11 +5760,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
;
; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: addiw a2, a0, 1
-; RV64IZHINX-NEXT: addi a0, a0, 1
-; RV64IZHINX-NEXT: fcvt.h.w a0, a0
-; RV64IZHINX-NEXT: sh a0, 0(a1)
-; RV64IZHINX-NEXT: mv a0, a2
+; RV64IZHINX-NEXT: addiw a0, a0, 1
+; RV64IZHINX-NEXT: fcvt.h.w a2, a0
+; RV64IZHINX-NEXT: sh a2, 0(a1)
; RV64IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
@@ -5776,11 +5774,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
;
; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: addiw a2, a0, 1
-; RV64IZDINXZHINX-NEXT: addi a0, a0, 1
-; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
-; RV64IZDINXZHINX-NEXT: sh a0, 0(a1)
-; RV64IZDINXZHINX-NEXT: mv a0, a2
+; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1
+; RV64IZDINXZHINX-NEXT: fcvt.h.w a2, a0
+; RV64IZDINXZHINX-NEXT: sh a2, 0(a1)
; RV64IZDINXZHINX-NEXT: ret
;
; RV32I-LABEL: fcvt_h_w_demanded_bits:
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