[llvm] [PPC]Optimize zeroing accumulator and spilling instructions into simple instructions (PR #96094)

[zhijian lin via llvm-commits]

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@@ -109,6 +109,93 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
           MachineFunctionProperties::Property::NoVRegs);
     }
 
+    // The funtion will simply the zeroing accumulator and spilling instrcutions
+    // into simple xxlxor and spilling instrcuctions.
+    // From:
+    // setaccz acci
+    // xxmfacc acci
+    // stxv vsr(i*4+0), D(1)
+    // stxv vsr(i*4+1), D-16(1)
+    // stxv vsr(i*4+2), D-32(1)
+    // stxv vsr(i*4+3), D-48(1)
+
+    // To:
+    // xxlxor vsr(i*4), 0, 0
+    // stxv vsr(i*4), D(1)
+    // stxv vsr(i*4), D-16(1)
+    // stxv vsr(i*4), D-32(1)
+    // stxv vsr(i*4), D-48(1)
+    bool
+    OptimizeZeroingAccumulatorSpilling(MachineBasicBlock &MBB,
+                                       const TargetRegisterInfo *TRI) const {
+      bool changed = false;
+      for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
+        if (BBI->getOpcode() != PPC::XXSETACCZ)
+          continue;
+
+        Register ACCZReg = BBI->getOperand(0).getReg();
+
+        DenseSet<MachineInstr *> InstrsToErase;
+        InstrsToErase.insert(&*BBI++);
+
----------------
diggerlin wrote:

> it is not necessary there must be 4 stores...
the patch is accumulator spill, it must has 4 stores.

> limiting the case that XXSETACCZ and XXMFACC must be adjacent is not a good idea...
OK, I will deal the XXSETACCZ and XXMFACC are not adjacent.

> limitting the case that the four stores must be followed XXMFACC is also not good.
the patch is accumulator spill, in the function  [PPCRegisterInfo::lowerACCSpilling](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp#L1313). the XXMFACC is followed by 4 store, but I can deal with XXMFACC is not followed by 4 store any ways.

> The loop structure also seems not able to handle case
I will deal with these case.

https://github.com/llvm/llvm-project/pull/96094