[llvm] [RISCV] Remove riscv-experimental-rv64-legal-i32. (PR #102509)

[Craig Topper via llvm-commits]

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@@ -119,8 +115,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
-  if (Subtarget.is64Bit() && RV64LegalI32)
-    addRegisterClass(MVT::i32, &RISCV::GPRRegClass);
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topperc wrote:

I think I have to remove some isel patterns first and those are shared with GISel.

https://github.com/llvm/llvm-project/pull/102509