[llvm] [AMDGPU] Clear load addresses between functions (PR #102515)

[Alexis Engelke via llvm-commits]

https://github.com/aengelke updated https://github.com/llvm/llvm-project/pull/102515

>From 70766b08a378f94de7fe2d49a15364c4595ebcaf Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Thu, 8 Aug 2024 18:13:29 +0000
Subject: [PATCH 1/2] [AMDGPU] Clear load addresses between functions

SLoadAddresses previously held data across different functions and used
these for dominance queries of blocks in different functions. This is
not intended; clear the state at the end of the pass.
---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 1315aa08557888..59a1eee8d4f91d 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -2611,6 +2611,7 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
     Modified = true;
   }
   ReleaseVGPRInsts.clear();
+  SLoadAddresses.clear();
 
   return Modified;
 }

>From 5c04fc85acf6ce852603672b5ca2050278240ff6 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Thu, 8 Aug 2024 18:33:44 +0000
Subject: [PATCH 2/2] Add test

---
 .../CodeGen/AMDGPU/waitcnt-multiple-funcs.mir | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir

diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
new file mode 100644
index 00000000000000..a65ec9c6765492
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
@@ -0,0 +1,41 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass si-insert-waitcnts -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+# CHECK-LABEL: name: t1
+# CHECK: liveins: $vgpr0
+name: t1
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+...
+
+---
+# CHECK-LABEL: name: t2
+# CHECK: liveins: $sgpr2_sgpr3
+# CHECK: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr2_sgpr3, 0, 0 :: (load (s64), addrspace 4)
+name: t2
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body: |
+  bb.0:
+    liveins: $sgpr2_sgpr3
+     $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr2_sgpr3, 0, 0 :: (load (s64), addrspace 4)
+...
+
+---
+# CHECK-LABEL: name: t3
+# CHECK:  liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3
+# CHECK:  $vgpr2 = BUFFER_ATOMIC_ADD_ADDR64_RTN $vgpr2, $vgpr0_vgpr1, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 1, implicit $exec :: (load store (s32), addrspace 1)
+name: t3
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3
+    $vgpr2 = BUFFER_ATOMIC_ADD_ADDR64_RTN $vgpr2, $vgpr0_vgpr1, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 1, implicit $exec :: (load store (s32), addrspace 1)
+...