[llvm] LSV: document hang reported in #37865 (PR #102479)

[Ramkumar Ramachandra via llvm-commits]

https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/102479

>From a0d06664b3d149df8d33502586a0f55ce3f03b48 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Thu, 8 Aug 2024 15:23:52 +0100
Subject: [PATCH 1/3] LSV: document hang reported in #37865

LoadStoreVectorizer hangs on certain examples, when its reorder function
goes into a cycle. Detect this cycle and explicitly forbid it, using an
assert, and document the resulting crash in a test-case under AArch64.
---
 .../Transforms/Vectorize/LoadStoreVectorizer.cpp    |  2 ++
 .../LoadStoreVectorizer/AArch64/pr37865.ll          | 13 +++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll

diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
index c91911ecad7456..c35ea431296b70 100644
--- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -216,6 +216,8 @@ void reorder(Instruction *I) {
       if (IM->getParent() != I->getParent())
         continue;
 
+      assert(IM != I && "Unexpected cycle while re-ordering instructions");
+
       if (!IM->comesBefore(I)) {
         InstructionsToMove.insert(IM);
         Worklist.push_back(IM);
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
new file mode 100644
index 00000000000000..d77c7256bfadbd
--- /dev/null
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
@@ -0,0 +1,13 @@
+; REQUIRES: asserts
+; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer -disable-output %s
+
+define i32 @load_cycle(ptr %x) {
+entry:
+  %gep.x.1 = getelementptr inbounds [2 x i32], ptr %x, i32 0, i32 1
+  %load.x.1 = load i32, ptr %gep.x.1
+  %rem = urem i32 %load.x.1, 1
+  %gep.x.2 = getelementptr inbounds [2 x i32], ptr %x, i32 %rem, i32 0
+  %load.x.2 = load i32, ptr %gep.x.2
+  %ret = add i32 %load.x.2, %load.x.1
+  ret i32 %ret
+}

>From 8bbe6f2557bd2ee1dff71fdd32c4ca7bc844eada Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Thu, 8 Aug 2024 18:25:31 +0100
Subject: [PATCH 2/3] LSV/test/pr37865: check assert message

---
 llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
index d77c7256bfadbd..8e5de719fe5945 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
@@ -2,6 +2,7 @@
 ; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer -disable-output %s
 
 define i32 @load_cycle(ptr %x) {
+; CHECK: Unexpected cycle while re-ordering instructions
 entry:
   %gep.x.1 = getelementptr inbounds [2 x i32], ptr %x, i32 0, i32 1
   %load.x.1 = load i32, ptr %gep.x.1

>From d89bf1dfccfe77292669bb95b562bb61b0d6b501 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Thu, 8 Aug 2024 18:35:11 +0100
Subject: [PATCH 3/3] LSV/test/pr37865: fix thinko; include FileCheck

---
 llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
index 8e5de719fe5945..833e70814c2917 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
@@ -1,5 +1,6 @@
 ; REQUIRES: asserts
-; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer -disable-output %s
+; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer \
+; RUN:   -disable-output %s 2>&1 | FileCheck %s
 
 define i32 @load_cycle(ptr %x) {
 ; CHECK: Unexpected cycle while re-ordering instructions