[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

[Sam Elliott via llvm-commits]

lenary wrote:

I do have some worries about the definition as-is, as the core in the repo has optional features (configurable at tape-out time). Reading the RP2350 datasheet, not all of the optional features for Hazard3 are enabled (and I'm of the opinion that the lack of arm-like `-mcpu=<core>+<optional stuff>+no<disabled stuff>` equivalent for RISC-V is a good thing) so I'm not sure exactly what we do here.

Maybe a better approach would be to abandon this PR and contribute a `-mcpu=raspberrypi-rp2350`, which would make it clearer which HDL configuration the compiler option specifically corresponds to? 

Happy to discuss this next week, thought I'd put some ideas about specific directions down in advance of that.

https://github.com/llvm/llvm-project/pull/102452