[llvm] c4e7728 - [Thumb2] Add regression test from #92576

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-08-08T11:39:05+01:00
New Revision: c4e77280f00370bb942098c13902f04c89033784

URL: https://github.com/llvm/llvm-project/commit/c4e77280f00370bb942098c13902f04c89033784
DIFF: https://github.com/llvm/llvm-project/commit/c4e77280f00370bb942098c13902f04c89033784.diff

LOG: [Thumb2] Add regression test from #92576

Ensure abds doesn't get truncated after type legalisation

Added: 
    llvm/test/CodeGen/Thumb2/abds-crash.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Thumb2/abds-crash.ll b/llvm/test/CodeGen/Thumb2/abds-crash.ll
new file mode 100644
index 00000000000000..2c872df178e977
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/abds-crash.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=thumbv7-- | FileCheck %s
+
+; Regression from #92576 - ensure abds doesn't get truncated after type legalisation
+
+define void @vp8_rd_pick_inter_mode() {
+; CHECK-LABEL: vp8_rd_pick_inter_mode:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    movs r4, #0
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    ldr r2, [r4]
+; CHECK-NEXT:    movs r1, #180
+; CHECK-NEXT:    str r0, [r1]
+; CHECK-NEXT:    movs r1, #188
+; CHECK-NEXT:    sxth r0, r0
+; CHECK-NEXT:    str r2, [r1]
+; CHECK-NEXT:    sxth r1, r2
+; CHECK-NEXT:    subs r0, r0, r1
+; CHECK-NEXT:    it mi
+; CHECK-NEXT:    rsbmi r0, r0, #0
+; CHECK-NEXT:    bl use
+; CHECK-NEXT:    ldrsh.w r0, [r4]
+; CHECK-NEXT:    ldrsh.w r1, [r0]
+; CHECK-NEXT:    subs r0, r1, r0
+; CHECK-NEXT:    it mi
+; CHECK-NEXT:    rsbmi r0, r0, #0
+; CHECK-NEXT:    bl use
+  %gep180 = getelementptr inbounds i8, ptr null, i32 180
+  %gep188 = getelementptr inbounds i8, ptr null, i32 188
+  %i0 = load i32, ptr poison, align 4
+  store i32 %i0, ptr %gep180, align 4
+  %i1 = load i32, ptr null, align 4
+  store i32 %i1, ptr %gep188, align 4
+  %sext.i0 = shl i32 %i0, 16
+  %sext.i1 = shl i32 %i1, 16
+  %conv.i0 = ashr exact i32 %sext.i0, 16
+  %conv.i1 = ashr exact i32 %sext.i1, 16
+  %sub.i01 = sub nsw i32 %conv.i0, %conv.i1
+  %i2 = call i32 @llvm.abs.i32(i32 %sub.i01, i1 true)
+  call fastcc void @use(i32 %i2)
+
+  %i3 = load i16, ptr poison, align 4
+  %i4 = load i16, ptr null, align 4
+  %conv.i3 = sext i16 %i3 to i32
+  %conv.i4 = sext i16 %i4 to i32
+  %sub.i34 = sub nsw i32 %conv.i3, %conv.i4
+  %i5 = call i32 @llvm.abs.i32(i32 %sub.i34, i1 true)
+  call fastcc void @use(i32 %i5)
+  unreachable
+}
+declare void @use(i32)
+
+attributes #0 = { "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,-aes,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fullfp16,-sha2,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" }
+attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+