[llvm] [RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (PR #102405)

[Fraser Cormack via llvm-commits]

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@@ -108,6 +108,9 @@ Changes to the RISC-V Backend
   fill value) rather than NOPs.
 * Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
 * ``-mcpu=sifive-p470`` was added.
+* Fixed length vector support using RVV instructions now requires VLEN>=64. This
+  mean Zve32x and Zve32f will also require Zvl64b. The prior support was largely
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frasercrmck wrote:

`means`

https://github.com/llvm/llvm-project/pull/102405