[llvm] [RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (PR #102405)

[Fraser Cormack via llvm-commits]

================
@@ -4,42 +4,21 @@
 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
 target triple = "riscv64"
 
-; We can't use scalable vectorization for Zvl32b due to RVVBitsPerBlock being
+; We can't use vectorize with Zvl32b due to RVVBitsPerBlock being
----------------
frasercrmck wrote:

`can't vectorize`?

https://github.com/llvm/llvm-project/pull/102405