[llvm] 5ce793e - [RISCV] Add TargetConstraintType=2 to VPseudoVNCVTF_RM_W. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-07T23:04:51-07:00
New Revision: 5ce793e7df1a31c588c7b7bded3020d7f1fd3b41

URL: https://github.com/llvm/llvm-project/commit/5ce793e7df1a31c588c7b7bded3020d7f1fd3b41
DIFF: https://github.com/llvm/llvm-project/commit/5ce793e7df1a31c588c7b7bded3020d7f1fd3b41.diff

LOG: [RISCV] Add TargetConstraintType=2 to VPseudoVNCVTF_RM_W. NFC

This doesn't do anything in upstream, but matches whats in our
downstream.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 86b30e836473d..c49066b06b837 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3731,7 +3731,8 @@ multiclass VPseudoVNCVTF_RM_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
     foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
-      defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e>,
+      defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e,
+                                    TargetConstraintType=2>,
                 SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
                            forcePassthruRead=true>;
   }