[llvm] baf7703 - `InOrderIssueStage` for llvm-mca should be generic over LSUnitBase (#101534)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 7 05:47:25 PDT 2024
Author: Chinmay Deshpande
Date: 2024-08-07T08:47:20-04:00
New Revision: baf77036f6244ee23f77e61f986f083dd2334b6a
URL: https://github.com/llvm/llvm-project/commit/baf77036f6244ee23f77e61f986f083dd2334b6a
DIFF: https://github.com/llvm/llvm-project/commit/baf77036f6244ee23f77e61f986f083dd2334b6a.diff
LOG: `InOrderIssueStage` for llvm-mca should be generic over LSUnitBase (#101534)
Other HardwareUnits (such as the
[Scheduler](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h#L71))
and Stages (such as
[RetireStage](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/MCA/Stages/RetireStage.h#L32))
are generic over `LSUnitBase` rather than the specialized `LSUnit`.
Added:
Modified:
llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
llvm/lib/MCA/Stages/InOrderIssueStage.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
index f9286acef9006..7fa7c89ad394e 100644
--- a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
+++ b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
@@ -21,7 +21,7 @@
namespace llvm {
namespace mca {
-class LSUnit;
+class LSUnitBase;
class RegisterFile;
struct StallInfo {
@@ -56,7 +56,7 @@ class InOrderIssueStage final : public Stage {
RegisterFile &PRF;
ResourceManager RM;
CustomBehaviour &CB;
- LSUnit &LSU;
+ LSUnitBase &LSU;
/// Instructions that were issued, but not executed yet.
SmallVector<InstRef, 4> IssuedInst;
@@ -113,7 +113,7 @@ class InOrderIssueStage final : public Stage {
public:
InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
- CustomBehaviour &CB, LSUnit &LSU);
+ CustomBehaviour &CB, LSUnitBase &LSU);
unsigned getIssueWidth() const;
bool isAvailable(const InstRef &) const override;
diff --git a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
index 8f720dbd82a76..30def19b1879a 100644
--- a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
+++ b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
@@ -45,7 +45,7 @@ void StallInfo::cycleEnd() {
InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI,
RegisterFile &PRF, CustomBehaviour &CB,
- LSUnit &LSU)
+ LSUnitBase &LSU)
: STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU),
NumIssued(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}
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